1. 11 Sep, 2019 1 commit
    • Daniel Drake's avatar
      Revert "mmc: sdhci: Remove unneeded quirk2 flag of O2 SD host controller" · 49baa01c
      Daniel Drake authored
      This reverts commit 414126f9
      
      .
      
      This commit broke eMMC storage access on a new consumer MiniPC based on
      AMD SoC, which has eMMC connected to:
      
      02:00.0 SD Host controller: O2 Micro, Inc. Device 8620 (rev 01) (prog-if 01)
      	Subsystem: O2 Micro, Inc. Device 0002
      
      During probe, several errors are seen including:
      
        mmc1: Got data interrupt 0x02000000 even though no data operation was in progress.
        mmc1: Timeout waiting for hardware interrupt.
        mmc1: error -110 whilst initialising MMC card
      
      Reverting this commit allows the eMMC storage to be detected & usable
      again.
      Signed-off-by: default avatarDaniel Drake <drake@endlessm.com>
      Fixes: 414126f9
      
       ("mmc: sdhci: Remove unneeded quirk2 flag of O2 SD host
      controller")
      Cc: stable@vger.kernel.org # v5.1+
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      49baa01c
  2. 18 Jun, 2019 2 commits
  3. 05 Jun, 2019 1 commit
  4. 25 Feb, 2019 3 commits
  5. 08 Oct, 2018 1 commit
    • Yu Zhao's avatar
      mmc: sdhci-pci-o2micro: Add quirk for O2 Micro dev 0x8620 rev 0x01 · 51698949
      Yu Zhao authored
      
      
      This device reports SDHCI_CLOCK_INT_STABLE even though it's not
      ready to take SDHCI_CLOCK_CARD_EN. The symptom is that reading
      SDHCI_CLOCK_CONTROL after enabling the clock shows absence of the
      bit from the register (e.g. expecting 0x0000fa07 = 0x0000fa03 |
      SDHCI_CLOCK_CARD_EN but only observed the first operand).
      
      mmc1: Timeout waiting for hardware cmd interrupt.
      mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
      mmc1: sdhci: Sys addr:  0x00000000 | Version:  0x00000603
      mmc1: sdhci: Blk size:  0x00000000 | Blk cnt:  0x00000000
      mmc1: sdhci: Argument:  0x00000000 | Trn mode: 0x00000000
      mmc1: sdhci: Present:   0x01ff0001 | Host ctl: 0x00000001
      mmc1: sdhci: Power:     0x0000000f | Blk gap:  0x00000000
      mmc1: sdhci: Wake-up:   0x00000000 | Clock:    0x0000fa03
      mmc1: sdhci: Timeout:   0x00000000 | Int stat: 0x00000000
      mmc1: sdhci: Int enab:  0x00ff0083 | Sig enab: 0x00ff0083
      mmc1: sdhci: AC12 err:  0x00000000 | Slot int: 0x00000000
      mmc1: sdhci: Caps:      0x25fcc8bf | Caps_1:   0x00002077
      mmc1: sdhci: Cmd:       0x00000000 | Max curr: 0x005800c8
      mmc1: sdhci: Resp[0]:   0x00000000 | Resp[1]:  0x00000000
      mmc1: sdhci: Resp[2]:   0x00000000 | Resp[3]:  0x00000000
      mmc1: sdhci: Host ctl2: 0x00000008
      mmc1: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x00000000
      mmc1: sdhci: ============================================
      
      The problem happens during wakeup from S3. Adding a delay quirk
      after power up reliably fixes the problem.
      Signed-off-by: default avatarYu Zhao <yuzhao@google.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      51698949
  6. 30 Jul, 2018 4 commits
  7. 30 Oct, 2017 1 commit
  8. 24 Apr, 2017 2 commits
  9. 26 Oct, 2015 2 commits
  10. 10 Nov, 2014 1 commit
  11. 22 May, 2014 1 commit
  12. 13 Jan, 2014 1 commit