1. 14 Sep, 2019 1 commit
  2. 28 Aug, 2019 1 commit
    • Anup Patel's avatar
      RISC-V: Fix FIXMAP area corruption on RV32 systems · a256f2e3
      Anup Patel authored
      
      
      Currently, various virtual memory areas of Linux RISC-V are organized
      in increasing order of their virtual addresses is as follows:
      1. User space area (This is lowest area and starts at 0x0)
      2. FIXMAP area
      3. VMALLOC area
      4. Kernel area (This is highest area and starts at PAGE_OFFSET)
      
      The maximum size of user space aread is represented by TASK_SIZE.
      
      On RV32 systems, TASK_SIZE is defined as VMALLOC_START which causes the
      user space area to overlap the FIXMAP area. This allows user space apps
      to potentially corrupt the FIXMAP area and kernel OF APIs will crash
      whenever they access corrupted FDT in the FIXMAP area.
      
      On RV64 systems, TASK_SIZE is set to fixed 256GB and no other areas
      happen to overlap so we don't see any FIXMAP area corruptions.
      
      This patch fixes FIXMAP area corruption on RV32 systems by setting
      TASK_SIZE to FIXADDR_START. We also move FIXADDR_TOP, FIXADDR_SIZE,
      and FIXADDR_START defines to asm/pgtable.h so that we can avoid cyclic
      header includes.
      
      Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
      Tested-by: default avatarAlistair Francis <alistair.francis@wdc.com>
      Reviewed-by: default avatarChristoph Hellwig <hch@lst.de>
      Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
      a256f2e3
  3. 14 Aug, 2019 4 commits
  4. 13 Aug, 2019 1 commit
    • Paul Walmsley's avatar
      riscv: fix flush_tlb_range() end address for flush_tlb_page() · eb936858
      Paul Walmsley authored
      
      
      The RISC-V kernel implementation of flush_tlb_page() when CONFIG_SMP
      is set is wrong.  It passes zero to flush_tlb_range() as the final
      address to flush, but it should be at least 'addr'.
      
      Some other Linux architecture ports use the beginning address to
      flush, plus PAGE_SIZE, as the final address to flush.  This might
      flush slightly more than what's needed, but it seems unlikely that
      being more clever would improve anything.  So let's just take that
      implementation for now.
      
      While here, convert the macro into a static inline function, primarily
      to avoid unintentional multiple evaluations of 'addr'.
      
      This second version of the patch fixes a coding style issue found by
      Christoph Hellwig <hch@lst.de>.
      
      Reported-by: default avatarAndreas Schwab <schwab@suse.de>
      Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
      Reviewed-by: default avatarChristoph Hellwig <hch@lst.de>
      eb936858
  5. 08 Aug, 2019 2 commits
  6. 31 Jul, 2019 3 commits
  7. 25 Jul, 2019 1 commit
    • Masahiro Yamada's avatar
      treewide: add "WITH Linux-syscall-note" to SPDX tag of uapi headers · d9c52522
      Masahiro Yamada authored
      UAPI headers licensed under GPL are supposed to have exception
      "WITH Linux-syscall-note" so that they can be included into non-GPL
      user space application code.
      
      The exception note is missing in some UAPI headers.
      
      Some of them slipped in by the treewide conversion commit b2441318
      ("License cleanup: add SPDX GPL-2.0 license identifier to files with
      no license"). Just run:
      
        $ git show --oneline b2441318
      
       -- arch/x86/include/uapi/asm/
      
      I believe they are not intentional, and should be fixed too.
      
      This patch was generated by the following script:
      
        git grep -l --not -e Linux-syscall-note --and -e SPDX-License-Identifier \
          -- :arch/*/include/uapi/asm/*.h :include/uapi/ :^*/Kbuild |
        while read file
        do
                sed -i -e '/[[:space:]]OR[[:space:]]/s/\(GPL-[^[:space:]]*\)/(\1 WITH Linux-syscall-note)/g' \
                -e '/[[:space:]]or[[:space:]]/s/\(GPL-[^[:space:]]*\)/(\1 WITH Linux-syscall-note)/g' \
                -e '/[[:space:]]OR[[:space:]]/!{/[[:space:]]or[[:space:]]/!s/\(GPL-[^[:space:]]*\)/\1 WITH Linux-syscall-note/g}' $file
        done
      
      After this patch is applied, there are 5 UAPI headers that do not contain
      "WITH Linux-syscall-note". They are kept untouched since this exception
      applies only to GPL variants.
      
        $ git grep --not -e Linux-syscall-note --and -e SPDX-License-Identifier \
          -- :arch/*/include/uapi/asm/*.h :include/uapi/ :^*/Kbuild
        include/uapi/drm/panfrost_drm.h:/* SPDX-License-Identifier: MIT */
        include/uapi/linux/batman_adv.h:/* SPDX-License-Identifier: MIT */
        include/uapi/linux/qemu_fw_cfg.h:/* SPDX-License-Identifier: BSD-3-Clause */
        include/uapi/linux/vbox_err.h:/* SPDX-License-Identifier: MIT */
        include/uapi/linux/virtio_iommu.h:/* SPDX-License-Identifier: BSD-3-Clause */
      
      Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      Reviewed-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      d9c52522
  8. 22 Jul, 2019 2 commits
  9. 19 Jul, 2019 1 commit
  10. 18 Jul, 2019 1 commit
    • Paul Walmsley's avatar
      riscv: fix build break after macro-to-function conversion in generic cacheflush.h · 2d69fbf3
      Paul Walmsley authored
      Commit c296d4dc ("asm-generic: fix a compilation warning")
      converted the various flush_*cache_* macros in
      asm-generic/cacheflush.h to static inline functions.  This breaks
      RISC-V builds, since RISC-V's cacheflush.h includes the generic
      cacheflush.h and then undefines the macros to be overridden.
      
      Fix by copying the subset of the no-op functions that are reused from
      the generic cacheflush.h into the RISC-V cacheflush.h, and dropping
      the include of the generic cacheflush.h.
      
      Fixes: c296d4dc
      
       ("asm-generic: fix a compilation warning")
      Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
      Cc: Qian Cai <cai@lca.pw>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      2d69fbf3
  11. 17 Jul, 2019 1 commit
  12. 12 Jul, 2019 1 commit
    • Mike Rapoport's avatar
      riscv: switch to generic version of pte allocation · d1b46fe5
      Mike Rapoport authored
      The only difference between the generic and RISC-V implementation of PTE
      allocation is the usage of __GFP_RETRY_MAYFAIL for both kernel and user
      PTEs and the absence of __GFP_ACCOUNT for the user PTEs.
      
      The conversion to the generic version removes the __GFP_RETRY_MAYFAIL and
      ensures that GFP_ACCOUNT is used for the user PTE allocations.
      
      The pte_free() and pte_free_kernel() versions are identical to the generic
      ones and can be simply dropped.
      
      Link: http://lkml.kernel.org/r/1557296232-15361-13-git-send-email-rppt@linux.ibm.com
      
      
      Signed-off-by: default avatarMike Rapoport <rppt@linux.ibm.com>
      Reviewed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      Cc: Albert Ou <aou@eecs.berkeley.edu>
      Cc: Anshuman Khandual <anshuman.khandual@arm.com>
      Cc: Anton Ivanov <anton.ivanov@cambridgegreys.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Greentime Hu <green.hu@gmail.com>
      Cc: Guan Xuetao <gxt@pku.edu.cn>
      Cc: Guo Ren <guoren@kernel.org>
      Cc: Guo Ren <ren_guo@c-sky.com>
      Cc: Helge Deller <deller@gmx.de>
      Cc: Ley Foon Tan <lftan@altera.com>
      Cc: Matthew Wilcox <willy@infradead.org>
      Cc: Matt Turner <mattst88@gmail.com>
      Cc: Michael Ellerman <mpe@ellerman.id.au>
      Cc: Michal Hocko <mhocko@suse.com>
      Cc: Paul Burton <paul.burton@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Richard Kuo <rkuo@codeaurora.org>
      Cc: Richard Weinberger <richard@nod.at>
      Cc: Russell King <linux@armlinux.org.uk>
      Cc: Sam Creasey <sammy@sammy.net>
      Cc: Vincent Chen <deanbo422@gmail.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      d1b46fe5
  13. 11 Jul, 2019 1 commit
    • Atish Patra's avatar
      RISC-V: Add an Image header that boot loader can parse. · 0f327f2a
      Atish Patra authored
      
      
      Currently, the last stage boot loaders such as U-Boot can accept only
      uImage which is an unnecessary additional step in automating boot
      process.
      
      Add an image header that boot loader understands and boot Linux from
      flat Image directly.
      
      This header is based on ARM64 boot image header and provides an
      opportunity to combine both ARM64 & RISC-V image headers in future.
      
      Also make sure that PE/COFF header can co-exist in the same image so
      that EFI stub can be supported for RISC-V in future. EFI specification
      needs PE/COFF image header in the beginning of the kernel image in order
      to load it as an EFI application. In order to support EFI stub, code0
      should be replaced with "MZ" magic string and res4(at offset 0x3c)
      should point to the rest of the PE/COFF header (which will be added
      during EFI support).
      
      Tested on both QEMU and HiFive Unleashed using OpenSBI + U-Boot + Linux.
      
      Signed-off-by: default avatarAtish Patra <atish.patra@wdc.com>
      Reviewed-by: default avatarKarsten Merker <merker@debian.org>
      Tested-by: Karsten Merker <merker@debian.org> (QEMU+OpenSBI+U-Boot)
      Tested-by: Kevin Hilman <khilman@baylibre.com> (OpenSBI + U-Boot + Linux)
      [paul.walmsley@sifive.com: fixed whitespace in boot-image-header.txt;
       converted structure comment to kernel-doc format and added some detail]
      Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
      0f327f2a
  14. 09 Jul, 2019 1 commit
    • Anup Patel's avatar
      RISC-V: Setup initial page tables in two stages · 671f9a3e
      Anup Patel authored
      
      
      Currently, the setup_vm() does initial page table setup in one-shot
      very early before enabling MMU. Due to this, the setup_vm() has to map
      all possible kernel virtual addresses since it does not know size and
      location of RAM. This means we have kernel mappings for non-existent
      RAM and any buggy driver (or kernel) code doing out-of-bound access
      to RAM will not fault and cause underterministic behaviour.
      
      Further, the setup_vm() creates PMD mappings (i.e. 2M mappings) for
      RV64 systems. This means for PAGE_OFFSET=0xffffffe000000000 (i.e.
      MAXPHYSMEM_128GB=y), the setup_vm() will require 129 pages (i.e.
      516 KB) of memory for initial page tables which is never freed. The
      memory required for initial page tables will further increase if
      we chose a lower value of PAGE_OFFSET (e.g. 0xffffff0000000000)
      
      This patch implements two-staged initial page table setup, as follows:
      1. Early (i.e. setup_vm()): This stage maps kernel image and DTB in
      a early page table (i.e. early_pg_dir). The early_pg_dir will be used
      only by boot HART so it can be freed as-part of init memory free-up.
      2. Final (i.e. setup_vm_final()): This stage maps all possible RAM
      banks in the final page table (i.e. swapper_pg_dir). The boot HART
      will start using swapper_pg_dir at the end of setup_vm_final(). All
      non-boot HARTs directly use the swapper_pg_dir created by boot HART.
      
      We have following advantages with this new approach:
      1. Kernel mappings for non-existent RAM don't exists anymore.
      2. Memory consumed by initial page tables is now indpendent of the
      chosen PAGE_OFFSET.
      3. Memory consumed by initial page tables on RV64 system is 2 pages
      (i.e. 8 KB) which has significantly reduced and these pages will be
      freed as-part of the init memory free-up.
      
      The patch also provides a foundation for implementing strict kernel
      mappings where we protect kernel text and rodata using PTE permissions.
      
      Suggested-by: default avatarMike Rapoport <rppt@linux.ibm.com>
      Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
      [paul.walmsley@sifive.com: updated to apply; fixed a checkpatch warning]
      Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
      671f9a3e
  15. 05 Jul, 2019 1 commit
  16. 04 Jul, 2019 2 commits
  17. 03 Jul, 2019 1 commit
  18. 01 Jul, 2019 6 commits
  19. 26 Jun, 2019 3 commits
  20. 23 Jun, 2019 1 commit
  21. 20 Jun, 2019 1 commit
    • Yash Shah's avatar
      EDAC/sifive: Add EDAC platform driver for SiFive SoCs · 91abaeaa
      Yash Shah authored
      
      
      Add an EDAC driver for SiFive SoCs. The initial version supports ECC
      event monitoring and reporting through the EDAC framework for the SiFive
      L2 cache controller. It registers for notifier events from the L2 cache
      controller driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events.
      
       [ bp: Massage commit message. ]
      
      Signed-off-by: default avatarYash Shah <yash.shah@sifive.com>
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      Reviewed-by: James Morse's avatarJames Morse <james.morse@arm.com>
      Cc: Albert Ou <aou@eecs.berkeley.edu>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: linux-edac <linux-edac@vger.kernel.org>
      Cc: linux-riscv@lists.infradead.org
      Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
      Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: "Paul E. McKenney" <paulmck@linux.ibm.com>
      Cc: Paul Walmsley <paul.walmsley@sifive.com>
      Cc: sachin.ghadi@sifive.com
      Link: https://lkml.kernel.org/r/1557142026-15949-2-git-send-email-yash.shah@sifive.com
      91abaeaa
  22. 19 Jun, 2019 2 commits
  23. 17 Jun, 2019 2 commits