1. 27 Sep, 2019 1 commit
  2. 11 Sep, 2019 2 commits
    • Andrew Jeffery's avatar
      mmc: sdhci-of-aspeed: Depend on CONFIG_OF_ADDRESS · 72976643
      Andrew Jeffery authored
      Resolves the following build error reported by the 0-day bot:
          ERROR: "of_platform_device_create" [drivers/mmc/host/sdhci-of-aspeed.ko] undefined!
      SPARC does not set CONFIG_OF_ADDRESS so the symbol is missing. Depend on
      CONFIG_OF_ADDRESS to ensure the driver is only built for supported
      Fixes: 2d28dbe042f4 ("mmc: sdhci-of-aspeed: Add support for the ASPEED SD controller")
      Reported-by: default avatarkbuild test robot <lkp@intel.com>
      Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
    • Andrew Jeffery's avatar
      mmc: sdhci-of-aspeed: Add support for the ASPEED SD controller · bb7b8ec6
      Andrew Jeffery authored
      Add a minimal driver for ASPEED's SD controller, which exposes two
      The ASPEED design implements a common register set for the SDHCIs, and
      moves some of the standard configuration elements out to this common
      area (e.g. 8-bit mode, and card detect configuration which is not
      currently supported).
      The SD controller has a dedicated hardware interrupt that is shared
      between the slots. The common register set exposes information on which
      slot triggered the interrupt; early revisions of the patch introduced an
      irqchip for the register, but reality is it doesn't behave as an
      irqchip, and the result fits awkwardly into the irqchip APIs. Instead
      I've taken the simple approach of using the IRQ as a shared IRQ with
      some minor performance impact for the second slot.
      Ryan was the original author of the patch - I've taken his work and
      massaged it to drop the irqchip support and rework the devicetree
      integration. The driver has been smoke tested under qemu against a
      minimal SD controller model and lightly tested on an ast2500-evb.
      Signed-off-by: default avatarRyan Chen <ryanchen.aspeed@gmail.com>
      Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
      Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
  3. 10 Jul, 2019 1 commit
  4. 21 May, 2019 1 commit
  5. 06 May, 2019 2 commits
  6. 15 Apr, 2019 2 commits
  7. 25 Feb, 2019 2 commits
  8. 14 Jan, 2019 2 commits
  9. 17 Dec, 2018 4 commits
  10. 15 Oct, 2018 1 commit
  11. 09 Oct, 2018 1 commit
    • Ludovic Barre's avatar
      mmc: mmci: add stm32 sdmmc variant · 46b723dd
      Ludovic Barre authored
      This patch adds a stm32 sdmmc variant, rev 1.1.
      Introduces a new Manufacturer id "0x53, ascii 'S' to define
      new stm32 sdmmc family with clean range of amba
      revision/configurations bits (corresponding to sdmmc_ver
      register with major/minor fields).
      Add 2 variants properties:
      -dma_lli, to enable link list support.
      -stm32_idmabsize_mask, defines the range of SDMMC_IDMABSIZER register
       which specify the number bytes per buffer.
      DT properties for sdmmc:
      -Indicate signal directions (only one property
       for d0dir, d123dir, cmd_dir)
      -Select command and data phase relation.
      -Select "clock in" from an external driver.
      Signed-off-by: default avatarLudovic Barre <ludovic.barre@st.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
  12. 08 Oct, 2018 4 commits
  13. 16 Jul, 2018 1 commit
  14. 21 May, 2018 1 commit
  15. 02 May, 2018 3 commits
  16. 26 Mar, 2018 1 commit
  17. 15 Mar, 2018 1 commit
  18. 02 Feb, 2018 1 commit
  19. 31 Jan, 2018 1 commit
  20. 16 Jan, 2018 1 commit
  21. 11 Jan, 2018 1 commit
    • Ard Biesheuvel's avatar
      mmc: sdhci_f_sdh30: add ACPI support · 90e1d8cc
      Ard Biesheuvel authored
      The Fujitsu SDH30 SDHCI controller may be described as a SCX0002 ACPI
      device on ACPI platforms incorporating the Socionext SynQuacer SoC.
      Given that mmc_of_parse() has already been made ACPI/DT agnostic,
      making the SDH30 driver ACPI capable is actually rather simple:
      all we need to do is make the call to sdhci_get_of_property() [which
      does not set any properties we care about] and the clock handling
      dependent on whether we are dealing with a DT device, and exposing
      the ACPI id via the platform_driver struct and the module metadata.
      Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
  22. 18 Dec, 2017 1 commit
  23. 15 Dec, 2017 1 commit
  24. 11 Dec, 2017 2 commits
  25. 29 Nov, 2017 1 commit
  26. 30 Oct, 2017 1 commit
    • Carlo Caione's avatar
      mmc: meson-mx-sdio: Add a driver for the Amlogic Meson8 and Meson8b SoCs · ed80a13b
      Carlo Caione authored
      Add a driver for the SDIO/MMC host found on the Amlogic Meson SoCs. This
      is an MMC controller which provides an interface between the application
      processor and various memory cards. It supports the SD specification
      v2.0 and the eMMC specification v4.41.
      The controller provides an internal "mux" which allows connecting up to
      three MMC devices to it. Only one device can be used at a time though
      since the registers are shared across all devices. The driver takes care
      of synchronizing access (similar to the dw_mmc driver).
      The maximum supported bus-width is 4-bits.
      Amlogic's GPL kernel sources call the corresponding driver "aml_sdio" to
      differentiate it from the other MMC controller in (at least the Meson8
      and Meson8b) the SoCs (they call the other drivers aml_sdhc and
      aml_sdhc_m8, which seem to support a bus-width of up to 8-bits). This
      means that there are three different MMC host controller IP blocks from
      Amlogic (each of them with completely own register layout and features):
      - "SDIO": 1 and 4 bit bus width, support for high-speed modes up to
        UHS-I SDR50, part of Meson6, Meson8 and Meson8b (the driver from this
        patch targets this controller)
      - "SDHC": 1, 4 and 8 bit bus width, compatible with standard iNAND
        interface, support for speeds up to HS200 and MMC spec up to version
        4.5x, part of Meson8 and Meson8b SoCs (there is no mainline driver
        for this controller yet)
      - "SDEMMC": 1, 4 and 8 bit bus width, support for speeds up to HS400
        and MMC spec up to version 5.0, part of the Meson GX (64-bit) SoCs
        (supported by the meson-gx MMC host driver)
      Signed-off-by: default avatarCarlo Caione <carlo@endlessm.com>
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>