1. 27 Sep, 2019 1 commit
  2. 11 Sep, 2019 1 commit
    • Andrew Jeffery's avatar
      mmc: sdhci-of-aspeed: Add support for the ASPEED SD controller · bb7b8ec6
      Andrew Jeffery authored
      
      
      Add a minimal driver for ASPEED's SD controller, which exposes two
      SDHCIs.
      
      The ASPEED design implements a common register set for the SDHCIs, and
      moves some of the standard configuration elements out to this common
      area (e.g. 8-bit mode, and card detect configuration which is not
      currently supported).
      
      The SD controller has a dedicated hardware interrupt that is shared
      between the slots. The common register set exposes information on which
      slot triggered the interrupt; early revisions of the patch introduced an
      irqchip for the register, but reality is it doesn't behave as an
      irqchip, and the result fits awkwardly into the irqchip APIs. Instead
      I've taken the simple approach of using the IRQ as a shared IRQ with
      some minor performance impact for the second slot.
      
      Ryan was the original author of the patch - I've taken his work and
      massaged it to drop the irqchip support and rework the devicetree
      integration. The driver has been smoke tested under qemu against a
      minimal SD controller model and lightly tested on an ast2500-evb.
      Signed-off-by: default avatarRyan Chen <ryanchen.aspeed@gmail.com>
      Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
      Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      bb7b8ec6
  3. 17 Dec, 2018 2 commits
  4. 09 Oct, 2018 1 commit
    • Ludovic Barre's avatar
      mmc: mmci: add stm32 sdmmc variant · 46b723dd
      Ludovic Barre authored
      
      
      This patch adds a stm32 sdmmc variant, rev 1.1.
      Introduces a new Manufacturer id "0x53, ascii 'S' to define
      new stm32 sdmmc family with clean range of amba
      revision/configurations bits (corresponding to sdmmc_ver
      register with major/minor fields).
      Add 2 variants properties:
      -dma_lli, to enable link list support.
      -stm32_idmabsize_mask, defines the range of SDMMC_IDMABSIZER register
       which specify the number bytes per buffer.
      
      DT properties for sdmmc:
      -Indicate signal directions (only one property
       for d0dir, d123dir, cmd_dir)
      -Select command and data phase relation.
      -Select "clock in" from an external driver.
      Signed-off-by: default avatarLudovic Barre <ludovic.barre@st.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      46b723dd
  5. 08 Oct, 2018 2 commits
    • Chunyan Zhang's avatar
      mmc: sdhci-sprd: Add Spreadtrum's initial host controller · fb8bd90f
      Chunyan Zhang authored
      
      
      This patch adds the initial support of Secure Digital Host Controller
      Interface compliant controller found in some latest Spreadtrum chipsets.
      This patch has been tested on the version of SPRD-R11 controller.
      
      R11 is a variant based on SD v4.0 specification.
      
      With this driver, R11 mmc can be initialized, can be mounted, read and
      written.
      Original-by: default avatarBillows Wu <billows.wu@unisoc.com>
      Signed-off-by: default avatarChunyan Zhang <chunyan.zhang@unisoc.com>
      Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      fb8bd90f
    • Masahiro Yamada's avatar
      mmc: uniphier-sd: add UniPhier SD/eMMC controller driver · 3fd784f7
      Masahiro Yamada authored
      Here is another TMIO MMC variant found in Socionext UniPhier SoCs.
      
      As commit b6147490
      
       ("mmc: tmio: split core functionality, DMA and
      MFD glue") said, these MMC controllers use the IP from Panasonic.
      
      However, the MMC controller in the TMIO (Toshiba Mobile IO) MFD chip
      was the first upstreamed user of this IP.  The common driver code
      for this IP is now called 'tmio-mmc-core' in Linux although it is a
      historical misnomer.
      
      Anyway, this driver select's MMC_TMIO_CORE to borrow the common code
      from tmio-mmc-core.c
      
      Older UniPhier SoCs (LD4, Pro4, sLD8) support the external DMA engine
      like renesas_sdhi_sys_dmac.c.  The difference is UniPhier SoCs use a
      single DMA channel whereas Renesas chips request separate channels for
      RX and TX.
      
      Newer UniPhier SoCs (Pro5 and later) support the internal DMA engine
      like renesas_sdhi_internal_dmac.c  The register map is almost the same,
      so I guess Renesas and Socionext use the same internal DMA hardware.
      The main difference is, the register offsets are doubled for Renesas.
      
                              Renesas      Socionext
                              SDHI         UniPhier
        DM_CM_DTRAN_MODE      0x820        0x410
        DM_CM_DTRAN_CTRL      0x828        0x414
        DM_CM_RST             0x830        0x418
        DM_CM_INFO1           0x840        0x420
        DM_CM_INFO1_MASK      0x848        0x424
        DM_CM_INFO2           0x850        0x428
        DM_CM_INFO2_MASK      0x858        0x42c
        DM_DTRAN_ADDR         0x880        0x440
        DM_DTRAN_ADDREX        ---         0x444
      
      This comes from the difference of host->bus_shift; 2 for Renesas SoCs,
      and 1 for UniPhier SoCs.  Also, the datasheet for UniPhier SoCs defines
      DM_DTRAN_ADDR and DM_DTRAN_ADDREX as two separate registers.
      
      It could be possible to factor out the DMA common code by introducing
      some hooks to cope with platform quirks, but this patch does not touch
      that for now.
      Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      Acked-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      3fd784f7
  6. 16 Jul, 2018 2 commits
  7. 21 May, 2018 1 commit
  8. 26 Mar, 2018 1 commit
  9. 15 Mar, 2018 1 commit
  10. 04 Jan, 2018 1 commit
  11. 15 Dec, 2017 1 commit
  12. 11 Dec, 2017 1 commit
  13. 02 Nov, 2017 1 commit
    • Greg Kroah-Hartman's avatar
      License cleanup: add SPDX GPL-2.0 license identifier to files with no license · b2441318
      Greg Kroah-Hartman authored
      Many source files in the tree are missing licensing information, which
      makes it harder for compliance tools to determine the correct license.
      
      By default all files without license information are under the default
      license of the kernel, which is GPL version 2.
      
      Update the files which contain no license information with the 'GPL-2.0'
      SPDX license identifier.  The SPDX identifier is a legally binding
      shorthand, which can be used instead of the full boiler plate text.
      
      This patch is based on work done by Thomas Gleixner and Kate Stewart and
      Philippe Ombredanne.
      
      How this work was done:
      
      Patches were generated and checked against linux-4.14-rc6 for a subset of
      the use cases:
       - file had no licensing information it it.
       - file was a */uapi/* one with no licensing information in it,
       - file was a */uapi/* one with existing licensing information,
      
      Further patches will be generated in subsequent months to fix up cases
      where non-standard...
      b2441318
  14. 30 Oct, 2017 1 commit
    • Carlo Caione's avatar
      mmc: meson-mx-sdio: Add a driver for the Amlogic Meson8 and Meson8b SoCs · ed80a13b
      Carlo Caione authored
      
      
      Add a driver for the SDIO/MMC host found on the Amlogic Meson SoCs. This
      is an MMC controller which provides an interface between the application
      processor and various memory cards. It supports the SD specification
      v2.0 and the eMMC specification v4.41.
      
      The controller provides an internal "mux" which allows connecting up to
      three MMC devices to it. Only one device can be used at a time though
      since the registers are shared across all devices. The driver takes care
      of synchronizing access (similar to the dw_mmc driver).
      The maximum supported bus-width is 4-bits.
      
      Amlogic's GPL kernel sources call the corresponding driver "aml_sdio" to
      differentiate it from the other MMC controller in (at least the Meson8
      and Meson8b) the SoCs (they call the other drivers aml_sdhc and
      aml_sdhc_m8, which seem to support a bus-width of up to 8-bits). This
      means that there are three different MMC host controller IP blocks from
      Amlogic (each of them with completely own register layout and features):
      - "SDIO": 1 and 4 bit bus width, support for high-speed modes up to
        UHS-I SDR50, part of Meson6, Meson8 and Meson8b (the driver from this
        patch targets this controller)
      - "SDHC": 1, 4 and 8 bit bus width, compatible with standard iNAND
        interface, support for speeds up to HS200 and MMC spec up to version
        4.5x, part of Meson8 and Meson8b SoCs (there is no mainline driver
        for this controller yet)
      - "SDEMMC": 1, 4 and 8 bit bus width, support for speeds up to HS400
        and MMC spec up to version 5.0, part of the Meson GX (64-bit) SoCs
        (supported by the meson-gx MMC host driver)
      Signed-off-by: default avatarCarlo Caione <carlo@endlessm.com>
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      ed80a13b
  15. 22 Sep, 2017 1 commit
  16. 30 Aug, 2017 2 commits
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  19. 13 Feb, 2017 1 commit
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  23. 29 Feb, 2016 1 commit
  24. 26 Oct, 2015 1 commit
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