pinctrl-st.c 47 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
/*
 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
 * Authors:
 *	Srinivas Kandagatla <srinivas.kandagatla@st.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
17
#include <linux/of_irq.h>
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
#include <linux/of_gpio.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/platform_device.h>
#include "core.h"

/* PIO Block registers */
/* PIO output */
#define REG_PIO_POUT			0x00
/* Set bits of POUT */
#define REG_PIO_SET_POUT		0x04
/* Clear bits of POUT */
#define REG_PIO_CLR_POUT		0x08
/* PIO input */
#define REG_PIO_PIN			0x10
/* PIO configuration */
#define REG_PIO_PC(n)			(0x20 + (n) * 0x10)
/* Set bits of PC[2:0] */
#define REG_PIO_SET_PC(n)		(0x24 + (n) * 0x10)
/* Clear bits of PC[2:0] */
#define REG_PIO_CLR_PC(n)		(0x28 + (n) * 0x10)
/* PIO input comparison */
#define REG_PIO_PCOMP			0x50
/* Set bits of PCOMP */
#define REG_PIO_SET_PCOMP		0x54
/* Clear bits of PCOMP */
#define REG_PIO_CLR_PCOMP		0x58
/* PIO input comparison mask */
#define REG_PIO_PMASK			0x60
/* Set bits of PMASK */
#define REG_PIO_SET_PMASK		0x64
/* Clear bits of PMASK */
#define REG_PIO_CLR_PMASK		0x68

#define ST_GPIO_DIRECTION_BIDIR	0x1
#define ST_GPIO_DIRECTION_OUT	0x2
#define ST_GPIO_DIRECTION_IN	0x4

/**
 *  Packed style retime configuration.
 *  There are two registers cfg0 and cfg1 in this style for each bank.
 *  Each field in this register is 8 bit corresponding to 8 pins in the bank.
 */
#define RT_P_CFGS_PER_BANK			2
#define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg)	REG_FIELD(reg, 0, 7)
#define RT_P_CFG0_DELAY_0_FIELD(reg)		REG_FIELD(reg, 16, 23)
#define RT_P_CFG0_DELAY_1_FIELD(reg)		REG_FIELD(reg, 24, 31)
#define RT_P_CFG1_INVERTCLK_FIELD(reg)		REG_FIELD(reg, 0, 7)
#define RT_P_CFG1_RETIME_FIELD(reg)		REG_FIELD(reg, 8, 15)
#define RT_P_CFG1_CLKNOTDATA_FIELD(reg)		REG_FIELD(reg, 16, 23)
#define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg)	REG_FIELD(reg, 24, 31)

/**
 * Dedicated style retime Configuration register
 * each register is dedicated per pin.
 */
#define RT_D_CFGS_PER_BANK		8
#define RT_D_CFG_CLK_SHIFT		0
#define RT_D_CFG_CLK_MASK		(0x3 << 0)
#define RT_D_CFG_CLKNOTDATA_SHIFT	2
#define RT_D_CFG_CLKNOTDATA_MASK	BIT(2)
#define RT_D_CFG_DELAY_SHIFT		3
#define RT_D_CFG_DELAY_MASK		(0xf << 3)
#define RT_D_CFG_DELAY_INNOTOUT_SHIFT	7
#define RT_D_CFG_DELAY_INNOTOUT_MASK	BIT(7)
#define RT_D_CFG_DOUBLE_EDGE_SHIFT	8
#define RT_D_CFG_DOUBLE_EDGE_MASK	BIT(8)
#define RT_D_CFG_INVERTCLK_SHIFT	9
#define RT_D_CFG_INVERTCLK_MASK		BIT(9)
#define RT_D_CFG_RETIME_SHIFT		10
#define RT_D_CFG_RETIME_MASK		BIT(10)

/*
 * Pinconf is represented in an opaque unsigned long variable.
 * Below is the bit allocation details for each possible configuration.
 * All the bit fields can be encapsulated into four variables
 * (direction, retime-type, retime-clk, retime-delay)
 *
 *	 +----------------+
 *[31:28]| reserved-3     |
 *	 +----------------+-------------
 *[27]   |	oe	  |		|
 *	 +----------------+		v
 *[26]   |	pu	  |	[Direction	]
 *	 +----------------+		^
 *[25]   |	od	  |		|
 *	 +----------------+-------------
 *[24]   | reserved-2     |
 *	 +----------------+-------------
 *[23]   |    retime      |		|
 *	 +----------------+		|
 *[22]   | retime-invclk  |		|
 *	 +----------------+		v
 *[21]   |retime-clknotdat|	[Retime-type	]
 *	 +----------------+		^
 *[20]   | retime-de      |		|
 *	 +----------------+-------------
 *[19:18]| retime-clk     |------>[Retime-Clk	]
 *	 +----------------+
 *[17:16]|  reserved-1    |
 *	 +----------------+
 *[15..0]| retime-delay   |------>[Retime Delay]
 *	 +----------------+
 */

#define ST_PINCONF_UNPACK(conf, param)\
				((conf >> ST_PINCONF_ ##param ##_SHIFT) \
				& ST_PINCONF_ ##param ##_MASK)

#define ST_PINCONF_PACK(conf, val, param)	(conf |=\
				((val & ST_PINCONF_ ##param ##_MASK) << \
					ST_PINCONF_ ##param ##_SHIFT))

/* Output enable */
#define ST_PINCONF_OE_MASK		0x1
#define ST_PINCONF_OE_SHIFT		27
#define ST_PINCONF_OE			BIT(27)
#define ST_PINCONF_UNPACK_OE(conf)	ST_PINCONF_UNPACK(conf, OE)
#define ST_PINCONF_PACK_OE(conf)	ST_PINCONF_PACK(conf, 1, OE)

/* Pull Up */
#define ST_PINCONF_PU_MASK		0x1
#define ST_PINCONF_PU_SHIFT		26
#define ST_PINCONF_PU			BIT(26)
#define ST_PINCONF_UNPACK_PU(conf)	ST_PINCONF_UNPACK(conf, PU)
#define ST_PINCONF_PACK_PU(conf)	ST_PINCONF_PACK(conf, 1, PU)

/* Open Drain */
#define ST_PINCONF_OD_MASK		0x1
#define ST_PINCONF_OD_SHIFT		25
#define ST_PINCONF_OD			BIT(25)
#define ST_PINCONF_UNPACK_OD(conf)	ST_PINCONF_UNPACK(conf, OD)
#define ST_PINCONF_PACK_OD(conf)	ST_PINCONF_PACK(conf, 1, OD)

#define ST_PINCONF_RT_MASK		0x1
#define ST_PINCONF_RT_SHIFT		23
#define ST_PINCONF_RT			BIT(23)
#define ST_PINCONF_UNPACK_RT(conf)	ST_PINCONF_UNPACK(conf, RT)
#define ST_PINCONF_PACK_RT(conf)	ST_PINCONF_PACK(conf, 1, RT)

#define ST_PINCONF_RT_INVERTCLK_MASK	0x1
#define ST_PINCONF_RT_INVERTCLK_SHIFT	22
#define ST_PINCONF_RT_INVERTCLK		BIT(22)
#define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
			ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
#define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
			ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)

#define ST_PINCONF_RT_CLKNOTDATA_MASK	0x1
#define ST_PINCONF_RT_CLKNOTDATA_SHIFT	21
#define ST_PINCONF_RT_CLKNOTDATA	BIT(21)
#define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf)	\
				ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
#define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
				ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)

#define ST_PINCONF_RT_DOUBLE_EDGE_MASK	0x1
#define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT	20
#define ST_PINCONF_RT_DOUBLE_EDGE	BIT(20)
#define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
				ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
#define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
				ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)

#define ST_PINCONF_RT_CLK_MASK		0x3
#define ST_PINCONF_RT_CLK_SHIFT		18
#define ST_PINCONF_RT_CLK		BIT(18)
#define ST_PINCONF_UNPACK_RT_CLK(conf)	ST_PINCONF_UNPACK(conf, RT_CLK)
#define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)

/* RETIME_DELAY in Pico Secs */
#define ST_PINCONF_RT_DELAY_MASK	0xffff
#define ST_PINCONF_RT_DELAY_SHIFT	0
#define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
#define ST_PINCONF_PACK_RT_DELAY(conf, val) \
				ST_PINCONF_PACK(conf, val, RT_DELAY)

#define ST_GPIO_PINS_PER_BANK	(8)
#define OF_GPIO_ARGS_MIN	(4)
#define OF_RT_ARGS_MIN		(2)

#define gpio_range_to_bank(chip) \
		container_of(chip, struct st_gpio_bank, range)

206
207
208
#define pc_to_bank(pc) \
		container_of(pc, struct st_gpio_bank, pc)

209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
enum st_retime_style {
	st_retime_style_none,
	st_retime_style_packed,
	st_retime_style_dedicated,
};

struct st_retime_dedicated {
	struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
};

struct st_retime_packed {
	struct regmap_field *clk1notclk0;
	struct regmap_field *delay_0;
	struct regmap_field *delay_1;
	struct regmap_field *invertclk;
	struct regmap_field *retime;
	struct regmap_field *clknotdata;
	struct regmap_field *double_edge;
};

struct st_pio_control {
	u32 rt_pin_mask;
	struct regmap_field *alt, *oe, *pu, *od;
	/* retiming */
	union {
		struct st_retime_packed		rt_p;
		struct st_retime_dedicated	rt_d;
	} rt;
};

struct st_pctl_data {
240
241
242
243
244
	const enum st_retime_style	rt_style;
	const unsigned int		*input_delays;
	const int			ninput_delays;
	const unsigned int		*output_delays;
	const int			noutput_delays;
245
	/* register offset information */
246
	const int alt, oe, pu, od, rt;
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
};

struct st_pinconf {
	int		pin;
	const char	*name;
	unsigned long	config;
	int		altfunc;
};

struct st_pmx_func {
	const char	*name;
	const char	**groups;
	unsigned	ngroups;
};

struct st_pctl_group {
	const char		*name;
	unsigned int		*pins;
	unsigned		npins;
	struct st_pinconf	*pin_conf;
};

269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
/*
 * Edge triggers are not supported at hardware level, it is supported by
 * software by exploiting the level trigger support in hardware.
 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
 * of each gpio pin in a GPIO bank.
 *
 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
 *
 * bit allocation per pin is:
 * Bits:  [0 - 3] | [4 - 7]  [8 - 11] ... ... ... ...  [ 28 - 31]
 *       --------------------------------------------------------
 *       |  pin-0  |  pin-2 | pin-3  | ... ... ... ... | pin -7 |
 *       --------------------------------------------------------
 *
 *  A pin can have one of following the values in its edge configuration field.
 *
 *	-------   ----------------------------
 *	[0-3]	- Description
 *	-------   ----------------------------
 *	0000	- No edge IRQ.
 *	0001	- Falling edge IRQ.
 *	0010	- Rising edge IRQ.
 *	0011	- Rising and Falling edge IRQ.
 *	-------   ----------------------------
 */

#define ST_IRQ_EDGE_CONF_BITS_PER_PIN	4
#define ST_IRQ_EDGE_MASK		0xf
#define ST_IRQ_EDGE_FALLING		BIT(0)
#define ST_IRQ_EDGE_RISING		BIT(1)
#define ST_IRQ_EDGE_BOTH		(BIT(0) | BIT(1))

#define ST_IRQ_RISING_EDGE_CONF(pin) \
	(ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))

#define ST_IRQ_FALLING_EDGE_CONF(pin) \
	(ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))

#define ST_IRQ_BOTH_EDGE_CONF(pin) \
	(ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))

#define ST_IRQ_EDGE_CONF(conf, pin) \
	(conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)

314
315
316
317
318
struct st_gpio_bank {
	struct gpio_chip		gpio_chip;
	struct pinctrl_gpio_range	range;
	void __iomem			*base;
	struct st_pio_control		pc;
319
320
	unsigned long			irq_edge_conf;
	spinlock_t                      lock;
321
322
323
324
325
326
327
328
329
330
331
332
333
};

struct st_pinctrl {
	struct device			*dev;
	struct pinctrl_dev		*pctl;
	struct st_gpio_bank		*banks;
	int				nbanks;
	struct st_pmx_func		*functions;
	int				nfunctions;
	struct st_pctl_group		*groups;
	int				ngroups;
	struct regmap			*regmap;
	const struct st_pctl_data	*data;
334
	void __iomem			*irqmux_base;
335
336
337
338
};

/* SOC specific data */

339
static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250,
340
			1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
341

342
343
344
345
346
347
static const struct st_pctl_data  stih407_data = {
	.rt_style       = st_retime_style_dedicated,
	.input_delays   = stih407_delays,
	.ninput_delays  = ARRAY_SIZE(stih407_delays),
	.output_delays  = stih407_delays,
	.noutput_delays = ARRAY_SIZE(stih407_delays),
348
349
350
	.alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
};

351
352
static const struct st_pctl_data stih407_flashdata = {
	.rt_style	= st_retime_style_none,
353
354
355
356
	.input_delays	= stih407_delays,
	.ninput_delays	= ARRAY_SIZE(stih407_delays),
	.output_delays	= stih407_delays,
	.noutput_delays = ARRAY_SIZE(stih407_delays),
357
358
359
360
361
362
363
	.alt = 0,
	.oe = -1, /* Not Available */
	.pu = -1, /* Not Available */
	.od = 60,
	.rt = 100,
};

364
365
366
367
368
369
370
371
372
373
static struct st_pio_control *st_get_pio_control(
			struct pinctrl_dev *pctldev, int pin)
{
	struct pinctrl_gpio_range *range =
			 pinctrl_find_gpio_range_from_pin(pctldev, pin);
	struct st_gpio_bank *bank = gpio_range_to_bank(range);

	return &bank->pc;
}

374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
/* Low level functions.. */
static inline int st_gpio_bank(int gpio)
{
	return gpio/ST_GPIO_PINS_PER_BANK;
}

static inline int st_gpio_pin(int gpio)
{
	return gpio%ST_GPIO_PINS_PER_BANK;
}

static void st_pinconf_set_config(struct st_pio_control *pc,
				int pin, unsigned long config)
{
	struct regmap_field *output_enable = pc->oe;
	struct regmap_field *pull_up = pc->pu;
	struct regmap_field *open_drain = pc->od;
	unsigned int oe_value, pu_value, od_value;
	unsigned long mask = BIT(pin);

394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
	if (output_enable) {
		regmap_field_read(output_enable, &oe_value);
		oe_value &= ~mask;
		if (config & ST_PINCONF_OE)
			oe_value |= mask;
		regmap_field_write(output_enable, oe_value);
	}

	if (pull_up) {
		regmap_field_read(pull_up, &pu_value);
		pu_value &= ~mask;
		if (config & ST_PINCONF_PU)
			pu_value |= mask;
		regmap_field_write(pull_up, pu_value);
	}

	if (open_drain) {
		regmap_field_read(open_drain, &od_value);
		od_value &= ~mask;
		if (config & ST_PINCONF_OD)
			od_value |= mask;
		regmap_field_write(open_drain, od_value);
	}
417
418
419
420
421
422
423
424
425
426
}

static void st_pctl_set_function(struct st_pio_control *pc,
				int pin_id, int function)
{
	struct regmap_field *alt = pc->alt;
	unsigned int val;
	int pin = st_gpio_pin(pin_id);
	int offset = pin * 4;

427
428
429
	if (!alt)
		return;

430
431
432
433
434
435
	regmap_field_read(alt, &val);
	val &= ~(0xf << offset);
	val |= function << offset;
	regmap_field_write(alt, val);
}

436
437
438
439
440
441
442
443
444
445
446
447
448
449
static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
{
	struct regmap_field *alt = pc->alt;
	unsigned int val;
	int offset = pin * 4;

	if (!alt)
		return 0;

	regmap_field_read(alt, &val);

	return (val >> offset) & 0xf;
}

450
451
452
static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
	const struct st_pctl_data *data, unsigned long config)
{
453
	const unsigned int *delay_times;
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
	int num_delay_times, i, closest_index = -1;
	unsigned int closest_divergence = UINT_MAX;

	if (ST_PINCONF_UNPACK_OE(config)) {
		delay_times = data->output_delays;
		num_delay_times = data->noutput_delays;
	} else {
		delay_times = data->input_delays;
		num_delay_times = data->ninput_delays;
	}

	for (i = 0; i < num_delay_times; i++) {
		unsigned int divergence = abs(delay - delay_times[i]);

		if (divergence == 0)
			return i;

		if (divergence < closest_divergence) {
			closest_divergence = divergence;
			closest_index = i;
		}
	}

	pr_warn("Attempt to set delay %d, closest available %d\n",
	     delay, delay_times[closest_index]);

	return closest_index;
}

static unsigned long st_pinconf_bit_to_delay(unsigned int index,
	const struct st_pctl_data *data, unsigned long output)
{
486
	const unsigned int *delay_times;
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
	int num_delay_times;

	if (output) {
		delay_times = data->output_delays;
		num_delay_times = data->noutput_delays;
	} else {
		delay_times = data->input_delays;
		num_delay_times = data->ninput_delays;
	}

	if (index < num_delay_times) {
		return delay_times[index];
	} else {
		pr_warn("Delay not found in/out delay list\n");
		return 0;
	}
}

static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
	int enable, int pin)
{
	unsigned int val = 0;

	regmap_field_read(field, &val);
	if (enable)
		val |= BIT(pin);
	else
		val &= ~BIT(pin);
	regmap_field_write(field, val);
}

static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
	struct st_pio_control *pc,	unsigned long config, int pin)
{
	const struct st_pctl_data *data = info->data;
	struct st_retime_packed *rt_p = &pc->rt.rt_p;
	unsigned int delay;

	st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
				ST_PINCONF_UNPACK_RT_CLK(config), pin);

	st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
				ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);

	st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
				ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);

	st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
				ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);

	st_regmap_field_bit_set_clear_pin(rt_p->retime,
				ST_PINCONF_UNPACK_RT(config), pin);

	delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
					data, config);
	/* 2 bit delay, lsb */
	st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
	/* 2 bit delay, msb */
	st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);

}

static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
	struct st_pio_control *pc, unsigned long config, int pin)
{
	int input	= ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
	int clk		= ST_PINCONF_UNPACK_RT_CLK(config);
	int clknotdata	= ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
	int double_edge	= ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
	int invertclk	= ST_PINCONF_UNPACK_RT_INVERTCLK(config);
	int retime	= ST_PINCONF_UNPACK_RT(config);

	unsigned long delay = st_pinconf_delay_to_bit(
			ST_PINCONF_UNPACK_RT_DELAY(config),
			info->data, config);
	struct st_retime_dedicated *rt_d = &pc->rt.rt_d;

	unsigned long retime_config =
		((clk) << RT_D_CFG_CLK_SHIFT) |
		((delay) << RT_D_CFG_DELAY_SHIFT) |
		((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
		((retime) << RT_D_CFG_RETIME_SHIFT) |
		((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
		((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
		((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);

	regmap_field_write(rt_d->rt[pin], retime_config);
}

static void st_pinconf_get_direction(struct st_pio_control *pc,
	int pin, unsigned long *config)
{
	unsigned int oe_value, pu_value, od_value;

581
582
583
584
585
	if (pc->oe) {
		regmap_field_read(pc->oe, &oe_value);
		if (oe_value & BIT(pin))
			ST_PINCONF_PACK_OE(*config);
	}
586

587
588
589
590
591
	if (pc->pu) {
		regmap_field_read(pc->pu, &pu_value);
		if (pu_value & BIT(pin))
			ST_PINCONF_PACK_PU(*config);
	}
592

593
594
595
596
597
	if (pc->od) {
		regmap_field_read(pc->od, &od_value);
		if (od_value & BIT(pin))
			ST_PINCONF_PACK_OD(*config);
	}
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
}

static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
	struct st_pio_control *pc,	int pin, unsigned long *config)
{
	const struct st_pctl_data *data = info->data;
	struct st_retime_packed *rt_p = &pc->rt.rt_p;
	unsigned int delay_bits, delay, delay0, delay1, val;
	int output = ST_PINCONF_UNPACK_OE(*config);

	if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
		ST_PINCONF_PACK_RT(*config);

	if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
		ST_PINCONF_PACK_RT_CLK(*config, 1);

	if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
		ST_PINCONF_PACK_RT_CLKNOTDATA(*config);

	if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
		ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);

	if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
		ST_PINCONF_PACK_RT_INVERTCLK(*config);

	regmap_field_read(rt_p->delay_0, &delay0);
	regmap_field_read(rt_p->delay_1, &delay1);
	delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
			(((delay0 & BIT(pin)) ? 1 : 0));
	delay =  st_pinconf_bit_to_delay(delay_bits, data, output);
	ST_PINCONF_PACK_RT_DELAY(*config, delay);

	return 0;
}

static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
	struct st_pio_control *pc,	int pin, unsigned long *config)
{
	unsigned int value;
	unsigned long delay_bits, delay, rt_clk;
	int output = ST_PINCONF_UNPACK_OE(*config);
	struct st_retime_dedicated *rt_d = &pc->rt.rt_d;

	regmap_field_read(rt_d->rt[pin], &value);

	rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
	ST_PINCONF_PACK_RT_CLK(*config, rt_clk);

	delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
	delay =  st_pinconf_bit_to_delay(delay_bits, info->data, output);
	ST_PINCONF_PACK_RT_DELAY(*config, delay);

	if (value & RT_D_CFG_CLKNOTDATA_MASK)
		ST_PINCONF_PACK_RT_CLKNOTDATA(*config);

	if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
		ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);

	if (value & RT_D_CFG_INVERTCLK_MASK)
		ST_PINCONF_PACK_RT_INVERTCLK(*config);

	if (value & RT_D_CFG_RETIME_MASK)
		ST_PINCONF_PACK_RT(*config);

	return 0;
}

/* GPIO related functions */

static inline void __st_gpio_set(struct st_gpio_bank *bank,
	unsigned offset, int value)
{
	if (value)
		writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
	else
		writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
}

static void st_gpio_direction(struct st_gpio_bank *bank,
		unsigned int gpio, unsigned int direction)
{
	int offset = st_gpio_pin(gpio);
	int i = 0;
	/**
	 * There are three configuration registers (PIOn_PC0, PIOn_PC1
	 * and PIOn_PC2) for each port. These are used to configure the
	 * PIO port pins. Each pin can be configured as an input, output,
	 * bidirectional, or alternative function pin. Three bits, one bit
	 * from each of the three registers, configure the corresponding bit of
	 * the port. Valid bit settings is:
	 *
	 * PC2		PC1		PC0	Direction.
	 * 0		0		0	[Input Weak pull-up]
	 * 0		0 or 1		1	[Bidirection]
	 * 0		1		0	[Output]
	 * 1		0		0	[Input]
	 *
	 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
	 * individually.
	 */
	for (i = 0; i <= 2; i++) {
		if (direction & BIT(i))
			writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
		else
			writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
	}
}

static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
{
708
	struct st_gpio_bank *bank = gpiochip_get_data(chip);
709
710
711
712
713
714

	return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
}

static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
715
	struct st_gpio_bank *bank = gpiochip_get_data(chip);
716
717
718
719
720
721
722
723
724
725
726
727
728
	__st_gpio_set(bank, offset, value);
}

static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_gpio_direction_input(chip->base + offset);

	return 0;
}

static int st_gpio_direction_output(struct gpio_chip *chip,
	unsigned offset, int value)
{
729
	struct st_gpio_bank *bank = gpiochip_get_data(chip);
730
731
732
733
734
735
736

	__st_gpio_set(bank, offset, value);
	pinctrl_gpio_direction_output(chip->base + offset);

	return 0;
}

737
738
static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
739
	struct st_gpio_bank *bank = gpiochip_get_data(chip);
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
	struct st_pio_control pc = bank->pc;
	unsigned long config;
	unsigned int direction = 0;
	unsigned int function;
	unsigned int value;
	int i = 0;

	/* Alternate function direction is handled by Pinctrl */
	function = st_pctl_get_pin_function(&pc, offset);
	if (function) {
		st_pinconf_get_direction(&pc, offset, &config);
		return !ST_PINCONF_UNPACK_OE(config);
	}

	/*
	 * GPIO direction is handled differently
	 * - See st_gpio_direction() above for an explanation
	 */
	for (i = 0; i <= 2; i++) {
		value = readl(bank->base + REG_PIO_PC(i));
		direction |= ((value >> offset) & 0x1) << i;
	}

	return (direction == ST_GPIO_DIRECTION_IN);
}

766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
/* Pinctrl Groups */
static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);

	return info->ngroups;
}

static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
				       unsigned selector)
{
	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);

	return info->groups[selector].name;
}

static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
	unsigned selector, const unsigned **pins, unsigned *npins)
{
	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);

	if (selector >= info->ngroups)
		return -EINVAL;

	*pins = info->groups[selector].pins;
	*npins = info->groups[selector].npins;

	return 0;
}

796
static inline const struct st_pctl_group *st_pctl_find_group_by_name(
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
	const struct st_pinctrl *info, const char *name)
{
	int i;

	for (i = 0; i < info->ngroups; i++) {
		if (!strcmp(info->groups[i].name, name))
			return &info->groups[i];
	}

	return NULL;
}

static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
	struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
{
	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	const struct st_pctl_group *grp;
	struct pinctrl_map *new_map;
	struct device_node *parent;
	int map_num, i;

	grp = st_pctl_find_group_by_name(info, np->name);
	if (!grp) {
		dev_err(info->dev, "unable to find group for node %s\n",
			np->name);
		return -EINVAL;
	}

	map_num = grp->npins + 1;
	new_map = devm_kzalloc(pctldev->dev,
				sizeof(*new_map) * map_num, GFP_KERNEL);
	if (!new_map)
		return -ENOMEM;

	parent = of_get_parent(np);
	if (!parent) {
		devm_kfree(pctldev->dev, new_map);
		return -EINVAL;
	}

	*map = new_map;
	*num_maps = map_num;
	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
	new_map[0].data.mux.function = parent->name;
	new_map[0].data.mux.group = np->name;
	of_node_put(parent);

	/* create config map per pin */
	new_map++;
	for (i = 0; i < grp->npins; i++) {
		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
		new_map[i].data.configs.group_or_pin =
				pin_get_name(pctldev, grp->pins[i]);
		new_map[i].data.configs.configs = &grp->pin_conf[i].config;
		new_map[i].data.configs.num_configs = 1;
	}
	dev_info(pctldev->dev, "maps: function %s group %s num %d\n",
		(*map)->data.mux.function, grp->name, map_num);

	return 0;
}

static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
			struct pinctrl_map *map, unsigned num_maps)
{
}

static struct pinctrl_ops st_pctlops = {
	.get_groups_count	= st_pctl_get_groups_count,
	.get_group_pins		= st_pctl_get_group_pins,
	.get_group_name		= st_pctl_get_group_name,
	.dt_node_to_map		= st_pctl_dt_node_to_map,
	.dt_free_map		= st_pctl_dt_free_map,
};

/* Pinmux */
static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);

	return info->nfunctions;
}

880
static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
	unsigned selector)
{
	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);

	return info->functions[selector].name;
}

static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
	unsigned selector, const char * const **grps, unsigned * const ngrps)
{
	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	*grps = info->functions[selector].groups;
	*ngrps = info->functions[selector].ngroups;

	return 0;
}

898
899
static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
			unsigned group)
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
{
	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	struct st_pinconf *conf = info->groups[group].pin_conf;
	struct st_pio_control *pc;
	int i;

	for (i = 0; i < info->groups[group].npins; i++) {
		pc = st_get_pio_control(pctldev, conf[i].pin);
		st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
	}

	return 0;
}

static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
			struct pinctrl_gpio_range *range, unsigned gpio,
			bool input)
{
	struct st_gpio_bank *bank = gpio_range_to_bank(range);
	/*
	 * When a PIO bank is used in its primary function mode (altfunc = 0)
	 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
	 * for the primary PIO functions are driven by the related PIO block
	 */
	st_pctl_set_function(&bank->pc, gpio, 0);
	st_gpio_direction(bank, gpio, input ?
		ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);

	return 0;
}

static struct pinmux_ops st_pmxops = {
	.get_functions_count	= st_pmx_get_funcs_count,
	.get_function_name	= st_pmx_get_fname,
	.get_function_groups	= st_pmx_get_groups,
935
	.set_mux		= st_pmx_set_mux,
936
	.gpio_set_direction	= st_pmx_set_gpio_direction,
937
	.strict			= true,
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
};

/* Pinconf  */
static void st_pinconf_get_retime(struct st_pinctrl *info,
	struct st_pio_control *pc, int pin, unsigned long *config)
{
	if (info->data->rt_style == st_retime_style_packed)
		st_pinconf_get_retime_packed(info, pc, pin, config);
	else if (info->data->rt_style == st_retime_style_dedicated)
		if ((BIT(pin) & pc->rt_pin_mask))
			st_pinconf_get_retime_dedicated(info, pc,
					pin, config);
}

static void st_pinconf_set_retime(struct st_pinctrl *info,
	struct st_pio_control *pc, int pin, unsigned long config)
{
	if (info->data->rt_style == st_retime_style_packed)
		st_pinconf_set_retime_packed(info, pc, config, pin);
	else if (info->data->rt_style == st_retime_style_dedicated)
		if ((BIT(pin) & pc->rt_pin_mask))
			st_pinconf_set_retime_dedicated(info, pc,
							config, pin);
}

963
964
static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
			unsigned long *configs, unsigned num_configs)
965
966
967
968
{
	int pin = st_gpio_pin(pin_id);
	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
969
	int i;
970

971
972
973
974
	for (i = 0; i < num_configs; i++) {
		st_pinconf_set_config(pc, pin, configs[i]);
		st_pinconf_set_retime(info, pc, pin, configs[i]);
	} /* for each config */
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995

	return 0;
}

static int st_pinconf_get(struct pinctrl_dev *pctldev,
			     unsigned pin_id, unsigned long *config)
{
	int pin = st_gpio_pin(pin_id);
	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
	struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);

	*config = 0;
	st_pinconf_get_direction(pc, pin, config);
	st_pinconf_get_retime(info, pc, pin, config);

	return 0;
}

static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
				   struct seq_file *s, unsigned pin_id)
{
996
	struct st_pio_control *pc;
997
	unsigned long config;
998
	unsigned int function;
999
	int offset = st_gpio_pin(pin_id);
1000
	char f[16];