Commit ef991796 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.16 kernel cycle.
  Like with GPIO it is actually a bit calm this time.

  Core changes:

   - After lengthy discussions and partly due to my ignorance, we have
     merged a patch making pinctrl_force_default() and
     pinctrl_force_sleep() reprogram the states into the hardware of any
     hogged pins, even if they are already in the desired state.

     This only apply to hogged pins since groups of pins owned by
     drivers need to be managed by each driver, lest they could not do
     things like runtime PM and put pins to sleeping state even if the
     system as a whole is not in sleep.

  New drivers:

   - New driver for the Microsemi Ocelot SoC. This is used in ethernet
     switches.

   - The X-Powers AXP209 GPIO driver was extended to also deal with pin
     control and moved over from the GPIO subsystem. This circuit is a
     mixed-mode integrated circuit which is part of AllWinner designs.

   - New subdriver for the Qualcomm MSM8998 SoC, core of a high end
     mobile devices (phones) chipset.

   - New subdriver for the ST Microelectronics STM32MP157 MPU and
     STM32F769 MCU from the STM32 family.

   - New subdriver for the MediaTek MT7622 SoC. This is used for
     routers, repeater, gateways and such network infrastructure.

   - New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC
     has multimedia features and target "smart devices", I guess in-car
     entertainment, in-flight entertainment, industrial control panels
     etc.

  General improvements:

   - Incremental improvements on the SH-PFC subdrivers for things like
     the CAN bus.

   - Enable the glitch filter on Baytrail GPIOs used for interrupts.

   - Proper handling of pins to GPIO ranges on the Semtec SX150X

   - An IRQ setup ordering fix on MCP23S08.

   - A good set of janitorial coding style fixes"

* tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (102 commits)
  pinctrl: mcp23s08: fix irq setup order
  pinctrl: Forward declare struct device
  pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding
  pinctrl: stm32: add STM32F769 MCU support
  pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping
  pinctrl: sx150x: Register pinctrl before adding the gpiochip
  pinctrl: sx150x: Unregister the pinctrl on release
  pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe()
  pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show()
  pinctrl: pinmux: Use seq_putc() in pinmux_pins_show()
  pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show()
  pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call
  pinctrl: mediatek: mt7622: fix potential uninitialized value being returned
  pinctrl: uniphier: refactor drive strength get/set functions
  pinctrl: imx7ulp: constify struct imx_cfg_params_decode
  pinctrl: imx: constify struct imx_pinctrl_soc_info
  pinctrl: imx7d: simplify imx7d_pinctrl_probe
  pinctrl: imx: use struct imx_pinctrl_soc_info as a const
  pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly.
  pinctrl: qcom: Add msm8998 pinctrl driver
  ...
parents bf644990 02e389e6
......@@ -17,6 +17,9 @@ and generic pin config nodes.
Supported configurations:
- skew-delay is supported on the Ethernet pins
- drive-strength with 4, 8, 12 or 16 mA as argument is supported for
entire groups on the groups "idegrp", "gmii_gmac0_grp", "gmii_gmac1_grp"
and "pcigrp".
Example:
......
......@@ -4,7 +4,8 @@ Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx6ul-iomuxc"
- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
"fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
......
Microsemi Ocelot pin controller Device Tree Bindings
----------------------------------------------------
Required properties:
- compatible : Should be "mscc,ocelot-pinctrl"
- reg : Address and length of the register set for the device
- gpio-controller : Indicates this device is a GPIO controller
- #gpio-cells : Must be 2.
The first cell is the pin number and the
second cell specifies GPIO flags, as defined in
<dt-bindings/gpio/gpio.h>.
- gpio-ranges : Range of pins managed by the GPIO controller.
The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
configuration documented in pinctrl-bindings.txt.
The following generic properties are supported:
- function
- pins
Example:
gpio: pinctrl@71070034 {
compatible = "mscc,ocelot-pinctrl";
reg = <0x71070034 0x28>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 22>;
uart_pins: uart-pins {
pins = "GPIO_6", "GPIO_7";
function = "uart";
};
uart2_pins: uart2-pins {
pins = "GPIO_12", "GPIO_13";
function = "uart2";
};
};
== MediaTek MT7622 pinctrl controller ==
Required properties for the root node:
- compatible: Should be one of the following
"mediatek,mt7622-pinctrl" for MT7622 SoC
- reg: offset and length of the pinctrl space
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be two. The first cell is the pin number and the
second is the GPIO flags.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
MT7622 pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, slew rate, etc.
We support 2 types of configuration nodes. Those nodes can be either pinmux
nodes or pinconf nodes. Each configuration node can consist of multiple nodes
describing the pinmux and pinconf options.
The name of each subnode doesn't matter as long as it is unique; all subnodes
should be enumerated and processed purely based on their content.
== pinmux nodes content ==
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinmux subnode:
Required properties are:
- groups: An array of strings. Each string contains the name of a group.
Valid values for these names are listed below.
- function: A string containing the name of the function to mux to the
group. Valid values for function names are listed below.
== pinconf nodes content ==
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinconf subnode:
Required properties are:
- pins: An array of strings. Each string contains the name of a pin.
Valid values for these names are listed below.
- groups: An array of strings. Each string contains the name of a group.
Valid values for these names are listed below.
Optional properies are:
bias-disable, bias-pull, bias-pull-down, input-enable,
input-schmitt-enable, input-schmitt-disable, output-enable
output-low, output-high, drive-strength, slew-rate
Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for
slower slew rate respectively.
Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA.
The following specific properties as defined are valid to specify in a pinconf
subnode:
Optional properties are:
- mediatek,tdsel: An integer describing the steps for output level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments are from 0
to 15.
- mediatek,rdsel: An integer describing the steps for input level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments are from 0
to 63.
== Valid values for pins, function and groups on MT7622 ==
Valid values for pins are:
pins can be referenced via the pin names as the below table shown and the
related physical number is also put ahead of those names which helps cross
references to pins between groups to know whether pins assignment conflict
happens among devices try to acquire those available pins.
Pin #: Valid values for pins
-----------------------------
PIN 0: "GPIO_A"
PIN 1: "I2S1_IN"
PIN 2: "I2S1_OUT"
PIN 3: "I2S_BCLK"
PIN 4: "I2S_WS"
PIN 5: "I2S_MCLK"
PIN 6: "TXD0"
PIN 7: "RXD0"
PIN 8: "SPI_WP"
PIN 9: "SPI_HOLD"
PIN 10: "SPI_CLK"
PIN 11: "SPI_MOSI"
PIN 12: "SPI_MISO"
PIN 13: "SPI_CS"
PIN 14: "I2C_SDA"
PIN 15: "I2C_SCL"
PIN 16: "I2S2_IN"
PIN 17: "I2S3_IN"
PIN 18: "I2S4_IN"
PIN 19: "I2S2_OUT"
PIN 20: "I2S3_OUT"
PIN 21: "I2S4_OUT"
PIN 22: "GPIO_B"
PIN 23: "MDC"
PIN 24: "MDIO"
PIN 25: "G2_TXD0"
PIN 26: "G2_TXD1"
PIN 27: "G2_TXD2"
PIN 28: "G2_TXD3"
PIN 29: "G2_TXEN"
PIN 30: "G2_TXC"
PIN 31: "G2_RXD0"
PIN 32: "G2_RXD1"
PIN 33: "G2_RXD2"
PIN 34: "G2_RXD3"
PIN 35: "G2_RXDV"
PIN 36: "G2_RXC"
PIN 37: "NCEB"
PIN 38: "NWEB"
PIN 39: "NREB"
PIN 40: "NDL4"
PIN 41: "NDL5"
PIN 42: "NDL6"
PIN 43: "NDL7"
PIN 44: "NRB"
PIN 45: "NCLE"
PIN 46: "NALE"
PIN 47: "NDL0"
PIN 48: "NDL1"
PIN 49: "NDL2"
PIN 50: "NDL3"
PIN 51: "MDI_TP_P0"
PIN 52: "MDI_TN_P0"
PIN 53: "MDI_RP_P0"
PIN 54: "MDI_RN_P0"
PIN 55: "MDI_TP_P1"
PIN 56: "MDI_TN_P1"
PIN 57: "MDI_RP_P1"
PIN 58: "MDI_RN_P1"
PIN 59: "MDI_RP_P2"
PIN 60: "MDI_RN_P2"
PIN 61: "MDI_TP_P2"
PIN 62: "MDI_TN_P2"
PIN 63: "MDI_TP_P3"
PIN 64: "MDI_TN_P3"
PIN 65: "MDI_RP_P3"
PIN 66: "MDI_RN_P3"
PIN 67: "MDI_RP_P4"
PIN 68: "MDI_RN_P4"
PIN 69: "MDI_TP_P4"
PIN 70: "MDI_TN_P4"
PIN 71: "PMIC_SCL"
PIN 72: "PMIC_SDA"
PIN 73: "SPIC1_CLK"
PIN 74: "SPIC1_MOSI"
PIN 75: "SPIC1_MISO"
PIN 76: "SPIC1_CS"
PIN 77: "GPIO_D"
PIN 78: "WATCHDOG"
PIN 79: "RTS3_N"
PIN 80: "CTS3_N"
PIN 81: "TXD3"
PIN 82: "RXD3"
PIN 83: "PERST0_N"
PIN 84: "PERST1_N"
PIN 85: "WLED_N"
PIN 86: "EPHY_LED0_N"
PIN 87: "AUXIN0"
PIN 88: "AUXIN1"
PIN 89: "AUXIN2"
PIN 90: "AUXIN3"
PIN 91: "TXD4"
PIN 92: "RXD4"
PIN 93: "RTS4_N"
PIN 94: "CST4_N"
PIN 95: "PWM1"
PIN 96: "PWM2"
PIN 97: "PWM3"
PIN 98: "PWM4"
PIN 99: "PWM5"
PIN 100: "PWM6"
PIN 101: "PWM7"
PIN 102: "GPIO_E"
Valid values for function are:
"emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie",
"pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
Valid values for groups are:
additional data is put followingly with valid value allowing us to know which
applicable function and which relevant pins (in pin#) are able applied for that
group.
Valid value function pins (in pin#)
-------------------------------------------------------------------------
"emmc" "emmc" 40, 41, 42, 43, 44, 45,
47, 48, 49, 50
"emmc_rst" "emmc" 37
"esw" "eth" 51, 52, 53, 54, 55, 56,
57, 58, 59, 60, 61, 62,
63, 64, 65, 66, 67, 68,
69, 70
"esw_p0_p1" "eth" 51, 52, 53, 54, 55, 56,
57, 58
"esw_p2_p3_p4" "eth" 59, 60, 61, 62, 63, 64,
65, 66, 67, 68, 69, 70
"rgmii_via_esw" "eth" 59, 60, 61, 62, 63, 64,
65, 66, 67, 68, 69, 70
"rgmii_via_gmac1" "eth" 59, 60, 61, 62, 63, 64,
65, 66, 67, 68, 69, 70
"rgmii_via_gmac2" "eth" 25, 26, 27, 28, 29, 30,
31, 32, 33, 34, 35, 36
"mdc_mdio" "eth" 23, 24
"i2c0" "i2c" 14, 15
"i2c1_0" "i2c" 55, 56
"i2c1_1" "i2c" 73, 74
"i2c1_2" "i2c" 87, 88
"i2c2_0" "i2c" 57, 58
"i2c2_1" "i2c" 75, 76
"i2c2_2" "i2c" 89, 90
"i2s_in_mclk_bclk_ws" "i2s" 3, 4, 5
"i2s1_in_data" "i2s" 1
"i2s2_in_data" "i2s" 16
"i2s3_in_data" "i2s" 17
"i2s4_in_data" "i2s" 18
"i2s_out_mclk_bclk_ws" "i2s" 3, 4, 5
"i2s1_out_data" "i2s" 2
"i2s2_out_data" "i2s" 19
"i2s3_out_data" "i2s" 20
"i2s4_out_data" "i2s" 21
"ir_0_tx" "ir" 16
"ir_1_tx" "ir" 59
"ir_2_tx" "ir" 99
"ir_0_rx" "ir" 17
"ir_1_rx" "ir" 60
"ir_2_rx" "ir" 100
"ephy_leds" "led" 86, 91, 92, 93, 94
"ephy0_led" "led" 86
"ephy1_led" "led" 91
"ephy2_led" "led" 92
"ephy3_led" "led" 93
"ephy4_led" "led" 94
"wled" "led" 85
"par_nand" "flash" 37, 38, 39, 40, 41, 42,
43, 44, 45, 46, 47, 48,
49, 50
"snfi" "flash" 8, 9, 10, 11, 12, 13
"spi_nor" "flash" 8, 9, 10, 11, 12, 13
"pcie0_0_waken" "pcie" 14
"pcie0_1_waken" "pcie" 79
"pcie1_0_waken" "pcie" 14
"pcie0_0_clkreq" "pcie" 15
"pcie0_1_clkreq" "pcie" 80
"pcie1_0_clkreq" "pcie" 15
"pcie0_pad_perst" "pcie" 83
"pcie1_pad_perst" "pcie" 84
"pmic_bus" "pmic" 71, 72
"pwm_ch1_0" "pwm" 51
"pwm_ch1_1" "pwm" 73
"pwm_ch1_2" "pwm" 95
"pwm_ch2_0" "pwm" 52
"pwm_ch2_1" "pwm" 74
"pwm_ch2_2" "pwm" 96
"pwm_ch3_0" "pwm" 53
"pwm_ch3_1" "pwm" 75
"pwm_ch3_2" "pwm" 97
"pwm_ch4_0" "pwm" 54
"pwm_ch4_1" "pwm" 67
"pwm_ch4_2" "pwm" 76
"pwm_ch4_3" "pwm" 98
"pwm_ch5_0" "pwm" 68
"pwm_ch5_1" "pwm" 77
"pwm_ch5_2" "pwm" 99
"pwm_ch6_0" "pwm" 69
"pwm_ch6_1" "pwm" 78
"pwm_ch6_2" "pwm" 81
"pwm_ch6_3" "pwm" 100
"pwm_ch7_0" "pwm" 70
"pwm_ch7_1" "pwm" 82
"pwm_ch7_2" "pwm" 101
"sd_0" "sd" 16, 17, 18, 19, 20, 21
"sd_1" "sd" 25, 26, 27, 28, 29, 30
"spic0_0" "spi" 63, 64, 65, 66
"spic0_1" "spi" 79, 80, 81, 82
"spic1_0" "spi" 67, 68, 69, 70
"spic1_1" "spi" 73, 74, 75, 76
"spic2_0_wp_hold" "spi" 8, 9
"spic2_0" "spi" 10, 11, 12, 13
"tdm_0_out_mclk_bclk_ws" "tdm" 8, 9, 10
"tdm_0_in_mclk_bclk_ws" "tdm" 11, 12, 13
"tdm_0_out_data" "tdm" 20
"tdm_0_in_data" "tdm" 21
"tdm_1_out_mclk_bclk_ws" "tdm" 57, 58, 59
"tdm_1_in_mclk_bclk_ws" "tdm" 60, 61, 62
"tdm_1_out_data" "tdm" 55
"tdm_1_in_data" "tdm" 56
"uart0_0_tx_rx" "uart" 6, 7
"uart1_0_tx_rx" "uart" 55, 56
"uart1_0_rts_cts" "uart" 57, 58
"uart1_1_tx_rx" "uart" 73, 74
"uart1_1_rts_cts" "uart" 75, 76
"uart2_0_tx_rx" "uart" 3, 4
"uart2_0_rts_cts" "uart" 1, 2
"uart2_1_tx_rx" "uart" 51, 52
"uart2_1_rts_cts" "uart" 53, 54
"uart2_2_tx_rx" "uart" 59, 60
"uart2_2_rts_cts" "uart" 61, 62
"uart2_3_tx_rx" "uart" 95, 96
"uart3_0_tx_rx" "uart" 57, 58
"uart3_1_tx_rx" "uart" 81, 82
"uart3_1_rts_cts" "uart" 79, 80
"uart4_0_tx_rx" "uart" 61, 62
"uart4_1_tx_rx" "uart" 91, 92
"uart4_1_rts_cts" "uart" 93, 94
"uart4_2_tx_rx" "uart" 97, 98
"uart4_2_rts_cts" "uart" 95, 96
"watchdog" "watchdog" 78
Example:
pio: pinctrl@10211000 {
compatible = "mediatek,mt7622-pinctrl";
reg = <0 0x10211000 0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
pinctrl_eth_default: eth-default {
mux-mdio {
groups = "mdc_mdio";
function = "eth";
drive-strength = <12>;
};
mux-gmac2 {
groups = "gmac2";
function = "eth";
drive-strength = <12>;
};
mux-esw {
groups = "esw";
function = "eth";
drive-strength = <8>;
};
conf-mdio {
pins = "MDC";
bias-pull-up;
};
};
};
Qualcomm MSM8998 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8998 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,msm8998-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins are:
gpio0-gpio149
Supports mux, bias and drive-strength
sdc2_clk, sdc2_cmd, sdc2_data
Supports bias and drive-strength
ufs_reset
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0,
atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1,
atest_usb10, atest_usb11, atest_usb12, atest_usb13,
audio_ref, bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a,
blsp10_spi_b, blsp11_i2c, blsp1_spi, blsp1_spi_a,
blsp1_spi_b, blsp2_spi, blsp9_spi, blsp_i2c1, blsp_i2c2,
blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7,
blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
blsp_spi11, blsp_spi12, blsp_uart1_a, blsp_uart1_b,
blsp_uart2_a, blsp_uart2_b, blsp_uart3_a, blsp_uart3_b,
blsp_uart7_a, blsp_uart7_b, blsp_uart8, blsp_uart8_a,
blsp_uart8_b, blsp_uart9_a, blsp_uart9_b, blsp_uim1_a,
blsp_uim1_b, blsp_uim2_a, blsp_uim2_b, blsp_uim3_a,
blsp_uim3_b, blsp_uim7_a, blsp_uim7_b, blsp_uim8_a,
blsp_uim8_b, blsp_uim9_a, blsp_uim9_b, bt_reset,
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
cri_trng0, cri_trng1, dbg_out, ddr_bist, edp_hot, edp_lcd,
gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b, gcc_gp3_a,
gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv,
isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus,
m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte,
nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag,
pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc,
pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b,
qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable,
qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41,
sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu,
spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1,
tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0,
vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1,
wlan2_adc0, wlan2_adc1,
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@03400000 {
compatible = "qcom,msm8998-pinctrl";
reg = <0x03400000 0xc00000>;
interrupts = <0 208 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
uart_console_active: uart_console_active {
mux {
pins = "gpio4", "gpio5";
function = "blsp_uart8_a";
};
config {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-disable;
};
};
};
......@@ -24,6 +24,7 @@ Required Properties:
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.