intel_dp.c 206 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

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#include <linux/export.h>
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#include <linux/i2c.h>
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#include <linux/notifier.h>
#include <linux/reboot.h>
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#include <linux/slab.h>
#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_hdcp.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/i915_drm.h>
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#include "i915_debugfs.h"
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#include "i915_drv.h"
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#include "intel_atomic.h"
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#include "intel_audio.h"
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#include "intel_connector.h"
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#include "intel_ddi.h"
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#include "intel_dp.h"
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#include "intel_dp_link_training.h"
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#include "intel_dp_mst.h"
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#include "intel_dpio_phy.h"
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#include "intel_drv.h"
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#include "intel_fifo_underrun.h"
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#include "intel_hdcp.h"
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#include "intel_hdmi.h"
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#include "intel_hotplug.h"
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#include "intel_lspcon.h"
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#include "intel_lvds.h"
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#include "intel_panel.h"
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#include "intel_psr.h"
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#include "intel_sideband.h"
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#include "intel_vdsc.h"
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#define DP_DPRX_ESI_LEN 14
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/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440
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#define DP_DSC_MIN_SUPPORTED_BPC		8
#define DP_DSC_MAX_SUPPORTED_BPC		10
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/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE			2720000
#define DP_DSC_MAX_ENC_THROUGHPUT_0		340000
#define DP_DSC_MAX_ENC_THROUGHPUT_1		400000

/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
#define DP_DSC_FEC_OVERHEAD_FACTOR		976

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/* Compliance test status bits  */
#define INTEL_DP_RESOLUTION_SHIFT_MASK	0
#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)

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struct dp_link_dpll {
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	int clock;
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	struct dpll dpll;
};

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static const struct dp_link_dpll g4x_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
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	{ 162000,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ 270000,
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		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
	/*
	 * CHV requires to program fractional division for m2.
	 * m2 is stored in fixed point format using formula below
	 * (m2_int << 22) | m2_fraction
	 */
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	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
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		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
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	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
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		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
};
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/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};

/* With Single pipe configuration, HW is capable of supporting maximum
 * of 4 slices per line.
 */
static const u8 valid_dsc_slicecount[] = {1, 2, 4};

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/**
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 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
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 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
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bool intel_dp_is_edp(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_encoder *encoder,
			       const struct intel_crtc_state *old_crtc_state);
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static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
					   const struct intel_crtc_state *crtc_state);
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static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
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				      enum pipe pipe);
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static void intel_dp_unset_edid(struct intel_dp *intel_dp);
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/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
{
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	static const int dp_rates[] = {
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		162000, 270000, 540000, 810000
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	};
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	int i, max_rate;
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	max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
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	for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
		if (dp_rates[i] > max_rate)
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			break;
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		intel_dp->sink_rates[i] = dp_rates[i];
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	}
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	intel_dp->num_sink_rates = i;
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}

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/* Get length of rates array potentially limited by max_rate. */
static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
{
	int i;

	/* Limit results by potentially reduced max rate */
	for (i = 0; i < len; i++) {
		if (rates[len - i - 1] <= max_rate)
			return len - i;
	}

	return 0;
}

/* Get length of common rates array potentially limited by max_rate. */
static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
					  int max_rate)
{
	return intel_dp_rate_limit_len(intel_dp->common_rates,
				       intel_dp->num_common_rates, max_rate);
}

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/* Theoretical max between source and sink */
static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
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{
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	return intel_dp->common_rates[intel_dp->num_common_rates - 1];
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}

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static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
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	intel_wakeref_t wakeref;
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	u32 lane_info;

	if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
		return 4;

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	with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
		lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
			     DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
				DP_LANE_ASSIGNMENT_SHIFT(tc_port);
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	switch (lane_info) {
	default:
		MISSING_CASE(lane_info);
	case 1:
	case 2:
	case 4:
	case 8:
		return 1;
	case 3:
	case 12:
		return 2;
	case 15:
		return 4;
	}
}

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/* Theoretical max between source and sink */
static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
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{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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	int source_max = intel_dig_port->max_lanes;
	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
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	int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
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	return min3(source_max, sink_max, fia_max);
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}

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int intel_dp_max_lane_count(struct intel_dp *intel_dp)
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{
	return intel_dp->max_link_lane_count;
}

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int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	/* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
	return DIV_ROUND_UP(pixel_clock * bpp, 8);
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}

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int
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intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
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	/* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
	 * link rate that is generally expressed in Gbps. Since, 8 bits of data
	 * is transmitted every LS_Clk per lane, there is no need to account for
	 * the channel encoding that is done in the PHY layer here.
	 */

	return max_link_clock * max_lanes;
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}

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static int
intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	int max_dotclk = dev_priv->max_dotclk_freq;
	int ds_max_dotclk;

	int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;

	if (type != DP_DS_PORT_TYPE_VGA)
		return max_dotclk;

	ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
						    intel_dp->downstream_ports);

	if (ds_max_dotclk != 0)
		max_dotclk = min(max_dotclk, ds_max_dotclk);

	return max_dotclk;
}

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static int cnl_max_source_rate(struct intel_dp *intel_dp)
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{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
	enum port port = dig_port->base.port;

	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;

	/* Low voltage SKUs are limited to max of 5.4G */
	if (voltage == VOLTAGE_INFO_0_85V)
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		return 540000;
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	/* For this SKU 8.1G is supported in all ports */
	if (IS_CNL_WITH_PORT_F(dev_priv))
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		return 810000;
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	/* For other SKUs, max rate on ports A and D is 5.4G */
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	if (port == PORT_A || port == PORT_D)
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		return 540000;
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	return 810000;
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}

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static int icl_max_source_rate(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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	enum port port = dig_port->base.port;

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	if (intel_port_is_combophy(dev_priv, port) &&
	    !intel_dp_is_edp(intel_dp))
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		return 540000;

	return 810000;
}

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static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
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{
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	/* The values must be in increasing order */
	static const int cnl_rates[] = {
		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
	};
	static const int bxt_rates[] = {
		162000, 216000, 243000, 270000, 324000, 432000, 540000
	};
	static const int skl_rates[] = {
		162000, 216000, 270000, 324000, 432000, 540000
	};
	static const int hsw_rates[] = {
		162000, 270000, 540000
	};
	static const int g4x_rates[] = {
		162000, 270000
	};
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	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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	const struct ddi_vbt_port_info *info =
		&dev_priv->vbt.ddi_port_info[dig_port->base.port];
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	const int *source_rates;
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	int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
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	/* This should only be done once */
	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);

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	if (INTEL_GEN(dev_priv) >= 10) {
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		source_rates = cnl_rates;
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		size = ARRAY_SIZE(cnl_rates);
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		if (IS_GEN(dev_priv, 10))
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			max_rate = cnl_max_source_rate(intel_dp);
		else
			max_rate = icl_max_source_rate(intel_dp);
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	} else if (IS_GEN9_LP(dev_priv)) {
		source_rates = bxt_rates;
		size = ARRAY_SIZE(bxt_rates);
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	} else if (IS_GEN9_BC(dev_priv)) {
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		source_rates = skl_rates;
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		size = ARRAY_SIZE(skl_rates);
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	} else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
		   IS_BROADWELL(dev_priv)) {
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		source_rates = hsw_rates;
		size = ARRAY_SIZE(hsw_rates);
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	} else {
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		source_rates = g4x_rates;
		size = ARRAY_SIZE(g4x_rates);
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	}

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	if (max_rate && vbt_max_rate)
		max_rate = min(max_rate, vbt_max_rate);
	else if (vbt_max_rate)
		max_rate = vbt_max_rate;

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	if (max_rate)
		size = intel_dp_rate_limit_len(source_rates, size, max_rate);

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	intel_dp->source_rates = source_rates;
	intel_dp->num_source_rates = size;
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}

static int intersect_rates(const int *source_rates, int source_len,
			   const int *sink_rates, int sink_len,
			   int *common_rates)
{
	int i = 0, j = 0, k = 0;

	while (i < source_len && j < sink_len) {
		if (source_rates[i] == sink_rates[j]) {
			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
				return k;
			common_rates[k] = source_rates[i];
			++k;
			++i;
			++j;
		} else if (source_rates[i] < sink_rates[j]) {
			++i;
		} else {
			++j;
		}
	}
	return k;
}

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/* return index of rate in rates array, or -1 if not found */
static int intel_dp_rate_index(const int *rates, int len, int rate)
{
	int i;

	for (i = 0; i < len; i++)
		if (rate == rates[i])
			return i;

	return -1;
}

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static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
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{
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	WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
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	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
						     intel_dp->num_source_rates,
						     intel_dp->sink_rates,
						     intel_dp->num_sink_rates,
						     intel_dp->common_rates);

	/* Paranoia, there should always be something in common. */
	if (WARN_ON(intel_dp->num_common_rates == 0)) {
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		intel_dp->common_rates[0] = 162000;
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		intel_dp->num_common_rates = 1;
	}
}

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static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
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				       u8 lane_count)
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{
	/*
	 * FIXME: we need to synchronize the current link parameters with
	 * hardware readout. Currently fast link training doesn't work on
	 * boot-up.
	 */
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	if (link_rate == 0 ||
	    link_rate > intel_dp->max_link_rate)
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		return false;

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	if (lane_count == 0 ||
	    lane_count > intel_dp_max_lane_count(intel_dp))
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		return false;

	return true;
}

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static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
						     int link_rate,
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						     u8 lane_count)
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{
	const struct drm_display_mode *fixed_mode =
		intel_dp->attached_connector->panel.fixed_mode;
	int mode_rate, max_rate;

	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
	max_rate = intel_dp_max_data_rate(link_rate, lane_count);
	if (mode_rate > max_rate)
		return false;

	return true;
}

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int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
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					    int link_rate, u8 lane_count)
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{
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	int index;
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	index = intel_dp_rate_index(intel_dp->common_rates,
				    intel_dp->num_common_rates,
				    link_rate);
	if (index > 0) {
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		if (intel_dp_is_edp(intel_dp) &&
		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
							      intel_dp->common_rates[index - 1],
							      lane_count)) {
			DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
			return 0;
		}
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		intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
		intel_dp->max_link_lane_count = lane_count;
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	} else if (lane_count > 1) {
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		if (intel_dp_is_edp(intel_dp) &&
		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
							      intel_dp_max_common_rate(intel_dp),
							      lane_count >> 1)) {
			DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
			return 0;
		}
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		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
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		intel_dp->max_link_lane_count = lane_count >> 1;
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	} else {
		DRM_ERROR("Link Training Unsuccessful\n");
		return -1;
	}

	return 0;
}

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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	struct drm_i915_private *dev_priv = to_i915(connector->dev);
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	int max_dotclk;
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	u16 dsc_max_output_bpp = 0;
	u8 dsc_slice_count = 0;
539

540
541
542
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

543
	max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
544

545
	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
546
		if (mode->hdisplay > fixed_mode->hdisplay)
547
548
			return MODE_PANEL;

549
		if (mode->vdisplay > fixed_mode->vdisplay)
550
			return MODE_PANEL;
551
552

		target_clock = fixed_mode->clock;
553
554
	}

555
	max_link_clock = intel_dp_max_link_rate(intel_dp);
556
	max_lanes = intel_dp_max_lane_count(intel_dp);
557
558
559
560

	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

561
562
563
564
565
566
567
568
569
570
571
572
	/*
	 * Output bpp is stored in 6.4 format so right shift by 4 to get the
	 * integer value since we support only integer values of bpp.
	 */
	if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
	    drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
		if (intel_dp_is_edp(intel_dp)) {
			dsc_max_output_bpp =
				drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
			dsc_slice_count =
				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
								true);
573
		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
574
575
576
577
578
579
580
581
582
583
584
585
586
587
			dsc_max_output_bpp =
				intel_dp_dsc_get_output_bpp(max_link_clock,
							    max_lanes,
							    target_clock,
							    mode->hdisplay) >> 4;
			dsc_slice_count =
				intel_dp_dsc_get_slice_count(intel_dp,
							     target_clock,
							     mode->hdisplay);
		}
	}

	if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
	    target_clock > max_dotclk)
588
		return MODE_CLOCK_HIGH;
589
590
591
592

	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

593
594
595
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

596
597
598
	return MODE_OK;
}

599
u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
600
{
601
602
	int i;
	u32 v = 0;
603
604
605
606

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
607
		v |= ((u32)src[i]) << ((3 - i) * 8);
608
609
610
	return v;
}

611
static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
612
613
614
615
616
617
618
619
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

620
static void
621
intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
622
static void
623
intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
624
					      bool force_disable_vdd);
625
static void
626
intel_dp_pps_init(struct intel_dp *intel_dp);
627

628
629
static intel_wakeref_t
pps_lock(struct intel_dp *intel_dp)
630
{
631
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
632
	intel_wakeref_t wakeref;
633
634

	/*
635
	 * See intel_power_sequencer_reset() why we need
636
637
	 * a power domain reference here.
	 */
638
639
	wakeref = intel_display_power_get(dev_priv,
					  intel_aux_power_domain(dp_to_dig_port(intel_dp)));
640
641

	mutex_lock(&dev_priv->pps_mutex);
642
643

	return wakeref;
644
645
}

646
647
static intel_wakeref_t
pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
648
{
649
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
650
651

	mutex_unlock(&dev_priv->pps_mutex);
652
653
654
655
	intel_display_power_put(dev_priv,
				intel_aux_power_domain(dp_to_dig_port(intel_dp)),
				wakeref);
	return 0;
656
657
}

658
659
660
#define with_pps_lock(dp, wf) \
	for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))

661
662
663
static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
664
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
665
666
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum pipe pipe = intel_dp->pps_pipe;
667
668
669
	bool pll_enabled, release_cl_override = false;
	enum dpio_phy phy = DPIO_PHY(pipe);
	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
670
	u32 DP;
671
672

	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
673
		 "skipping pipe %c power sequencer kick due to port %c being active\n",
674
		 pipe_name(pipe), port_name(intel_dig_port->base.port)))
675
676
677
		return;

	DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
678
		      pipe_name(pipe), port_name(intel_dig_port->base.port));
679
680
681
682
683
684
685
686
687

	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
	DP |= DP_PORT_WIDTH(1);
	DP |= DP_LINK_TRAIN_PAT_1;

688
	if (IS_CHERRYVIEW(dev_priv))
689
690
691
		DP |= DP_PIPE_SEL_CHV(pipe);
	else
		DP |= DP_PIPE_SEL(pipe);
692

693
694
695
696
697
698
	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;

	/*
	 * The DPLL for the pipe must be enabled for this to work.
	 * So enable temporarily it if it's not already enabled.
	 */
699
	if (!pll_enabled) {
700
		release_cl_override = IS_CHERRYVIEW(dev_priv) &&
701
702
			!chv_phy_powergate_ch(dev_priv, phy, ch, true);

703
		if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
704
705
706
707
708
				     &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
			DRM_ERROR("Failed to force on pll for pipe %c!\n",
				  pipe_name(pipe));
			return;
		}
709
	}
710

711
712
713
	/*
	 * Similar magic as in intel_dp_enable_port().
	 * We _must_ do this port enable + disable trick
714
	 * to make this power sequencer lock onto the port.
715
716
717
718
719
720
721
722
723
724
	 * Otherwise even VDD force bit won't work.
	 */
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
725

726
	if (!pll_enabled) {
727
		vlv_force_pll_off(dev_priv, pipe);
728
729
730
731

		if (release_cl_override)
			chv_phy_powergate_ch(dev_priv, phy, ch, false);
	}
732
733
}

734
735
736
737
738
739
740
741
742
static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
{
	struct intel_encoder *encoder;
	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);

	/*
	 * We don't have power sequencer currently.
	 * Pick one that's not used by other ports.
	 */
743
744
	for_each_intel_dp(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765

		if (encoder->type == INTEL_OUTPUT_EDP) {
			WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
				intel_dp->active_pipe != intel_dp->pps_pipe);

			if (intel_dp->pps_pipe != INVALID_PIPE)
				pipes &= ~(1 << intel_dp->pps_pipe);
		} else {
			WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);

			if (intel_dp->active_pipe != INVALID_PIPE)
				pipes &= ~(1 << intel_dp->active_pipe);
		}
	}

	if (pipes == 0)
		return INVALID_PIPE;

	return ffs(pipes) - 1;
}

766
767
768
static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
769
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
770
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
771
	enum pipe pipe;
772

773
	lockdep_assert_held(&dev_priv->pps_mutex);
774

775
	/* We should never land here with regular DP ports */
776
	WARN_ON(!intel_dp_is_edp(intel_dp));
777

778
779
780
	WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
		intel_dp->active_pipe != intel_dp->pps_pipe);

781
782
783
	if (intel_dp->pps_pipe != INVALID_PIPE)
		return intel_dp->pps_pipe;

784
	pipe = vlv_find_free_pps(dev_priv);
785
786
787
788
789

	/*
	 * Didn't find one. This should not happen since there
	 * are two power sequencers and up to two eDP ports.
	 */
790
	if (WARN_ON(pipe == INVALID_PIPE))
791
		pipe = PIPE_A;
792

793
	vlv_steal_power_sequencer(dev_priv, pipe);
794
	intel_dp->pps_pipe = pipe;
795
796
797

	DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe),
798
		      port_name(intel_dig_port->base.port));
799
800

	/* init power sequencer on this pipe and port */
801
802
	intel_dp_init_panel_power_sequencer(intel_dp);
	intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
803

804
805
806
807
808
	/*
	 * Even vdd force doesn't work until we've made
	 * the power sequencer lock in on the port.
	 */
	vlv_power_sequencer_kick(intel_dp);
809
810
811
812

	return intel_dp->pps_pipe;
}

813
814
815
static int
bxt_power_sequencer_idx(struct intel_dp *intel_dp)
{
816
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
817
	int backlight_controller = dev_priv->vbt.backlight.controller;
818
819
820
821

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* We should never land here with regular DP ports */
822
	WARN_ON(!intel_dp_is_edp(intel_dp));
823
824

	if (!intel_dp->pps_reset)
825
		return backlight_controller;
826
827
828
829
830
831
832

	intel_dp->pps_reset = false;

	/*
	 * Only the HW needs to be reprogrammed, the SW state is fixed and
	 * has been setup during connector init.
	 */
833
	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
834

835
	return backlight_controller;
836
837
}

838
839
840
841
842
843
typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
			       enum pipe pipe);

static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
844
	return I915_READ(PP_STATUS(pipe)) & PP_ON;
845
846
847
848
849
}

static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
				enum pipe pipe)
{
850
	return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
851
852
853
854
855
856
857
}

static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
			 enum pipe pipe)
{
	return true;
}
858

859
static enum pipe
860
861
862
vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
		     enum port port,
		     vlv_pipe_check pipe_check)
863
864
{
	enum pipe pipe;
865
866

	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
867
		u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
868
			PANEL_PORT_SELECT_MASK;
869
870
871
872

		if (port_sel != PANEL_PORT_SELECT_VLV(port))
			continue;

873
874
875
		if (!pipe_check(dev_priv, pipe))
			continue;

876
		return pipe;
877
878
	}

879
880
881
882
883
884
	return INVALID_PIPE;
}

static void
vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
{
885
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
886
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
887
	enum port port = intel_dig_port->base.port;
888
889
890
891

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* try to find a pipe with this port selected */
892
893
894
895
896
897
898
899
900
901
902
	/* first pick one where the panel is on */
	intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
						  vlv_pipe_has_pp_on);
	/* didn't find one? pick one where vdd is on */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_has_vdd_on);
	/* didn't find one? pick one with just the correct port */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_any);
903
904
905
906
907
908

	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
	if (intel_dp->pps_pipe == INVALID_PIPE) {
		DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
			      port_name(port));
		return;
909
910
	}

911
912
913
	DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
		      port_name(port), pipe_name(intel_dp->pps_pipe));

914
915
	intel_dp_init_panel_power_sequencer(intel_dp);
	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
916
917
}

918
void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
919
920
921
{
	struct intel_encoder *encoder;

922
	if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
923
		    !IS_GEN9_LP(dev_priv)))
924
925
926
927
928
929
930
931
932
933
934
935
		return;

	/*
	 * We can't grab pps_mutex here due to deadlock with power_domain
	 * mutex when power_domain functions are called while holding pps_mutex.
	 * That also means that in order to use pps_pipe the code needs to
	 * hold both a power domain reference and pps_mutex, and the power domain
	 * reference get/put must be done while _not_ holding pps_mutex.
	 * pps_{lock,unlock}() do these steps in the correct order, so one
	 * should use them always.
	 */

936
937
	for_each_intel_dp(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
938

939
940
941
942
943
		WARN_ON(intel_dp->active_pipe != INVALID_PIPE);

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

944
		if (IS_GEN9_LP(dev_priv))
945
946
947
			intel_dp->pps_reset = true;
		else
			intel_dp->pps_pipe = INVALID_PIPE;
948
	}
949
950
}

951
952
953
954
955
956
957
958
struct pps_registers {
	i915_reg_t pp_ctrl;
	i915_reg_t pp_stat;
	i915_reg_t pp_on;
	i915_reg_t pp_off;
	i915_reg_t pp_div;
};

959
static void intel_pps_get_registers(struct intel_dp *intel_dp,
960
961
				    struct pps_registers *regs)
{
962
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
963
964
	int pps_idx = 0;

965
966
	memset(regs, 0, sizeof(*regs));

967
	if (IS_GEN9_LP(dev_priv))
968
969
970
		pps_idx = bxt_power_sequencer_idx(intel_dp);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		pps_idx = vlv_power_sequencer_pipe(intel_dp);
971

972
973
974
975
	regs->pp_ctrl = PP_CONTROL(pps_idx);
	regs->pp_stat = PP_STATUS(pps_idx);
	regs->pp_on = PP_ON_DELAYS(pps_idx);
	regs->pp_off = PP_OFF_DELAYS(pps_idx);
976
977

	/* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
978
	if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
979
980
		regs->pp_div = INVALID_MMIO_REG;
	else
981
		regs->pp_div = PP_DIVISOR(pps_idx);
982
983
}

984
985
static i915_reg_t
_pp_ctrl_reg(struct intel_dp *intel_dp)
986
{
987
	struct pps_registers regs;
988

989
	intel_pps_get_registers(intel_dp, &regs);
990
991

	return regs.pp_ctrl;
992
993
}

994
995
static i915_reg_t
_pp_stat_reg(struct intel_dp *intel_dp)
996
{
997
	struct pps_registers regs;
998

999
	intel_pps_get_registers(intel_dp, &regs);
1000

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