intel_display.c 491 KB
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/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

#include <linux/i2c.h>
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#include <linux/input.h>
#include <linux/intel-iommu.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/dma-resv.h>
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#include <linux/slab.h>
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#include <linux/vgaarb.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_atomic_uapi.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_edid.h>
#include <drm/drm_fourcc.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_rect.h>
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#include <drm/i915_drm.h>

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#include "display/intel_crt.h"
#include "display/intel_ddi.h"
#include "display/intel_dp.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
#include "display/intel_gmbus.h"
#include "display/intel_hdmi.h"
#include "display/intel_lvds.h"
#include "display/intel_sdvo.h"
#include "display/intel_tv.h"
#include "display/intel_vdsc.h"

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#include "i915_drv.h"
#include "i915_trace.h"
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#include "intel_acpi.h"
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#include "intel_atomic.h"
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#include "intel_atomic_plane.h"
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#include "intel_bw.h"
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#include "intel_cdclk.h"
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#include "intel_color.h"
#include "intel_display_types.h"
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#include "intel_fbc.h"
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#include "intel_fbdev.h"
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#include "intel_fifo_underrun.h"
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#include "intel_frontbuffer.h"
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#include "intel_hdcp.h"
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#include "intel_hotplug.h"
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#include "intel_overlay.h"
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#include "intel_pipe_crc.h"
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#include "intel_pm.h"
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#include "intel_psr.h"
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#include "intel_quirks.h"
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#include "intel_sideband.h"
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#include "intel_sprite.h"
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#include "intel_tc.h"
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/* Primary plane formats for gen <= 3 */
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static const u32 i8xx_primary_formats[] = {
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	DRM_FORMAT_C8,
	DRM_FORMAT_RGB565,
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	DRM_FORMAT_XRGB1555,
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	DRM_FORMAT_XRGB8888,
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};

/* Primary plane formats for gen >= 4 */
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static const u32 i965_primary_formats[] = {
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	DRM_FORMAT_C8,
	DRM_FORMAT_RGB565,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_XRGB2101010,
	DRM_FORMAT_XBGR2101010,
};

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static const u64 i9xx_format_modifiers[] = {
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	I915_FORMAT_MOD_X_TILED,
	DRM_FORMAT_MOD_LINEAR,
	DRM_FORMAT_MOD_INVALID
};

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/* Cursor formats */
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static const u32 intel_cursor_formats[] = {
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	DRM_FORMAT_ARGB8888,
};

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static const u64 cursor_format_modifiers[] = {
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	DRM_FORMAT_MOD_LINEAR,
	DRM_FORMAT_MOD_INVALID
};

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static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
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				struct intel_crtc_state *pipe_config);
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static void ironlake_pch_clock_get(struct intel_crtc *crtc,
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				   struct intel_crtc_state *pipe_config);
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static int intel_framebuffer_init(struct intel_framebuffer *ifb,
				  struct drm_i915_gem_object *obj,
				  struct drm_mode_fb_cmd2 *mode_cmd);
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static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
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static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
					 const struct intel_link_m_n *m_n,
					 const struct intel_link_m_n *m2_n2);
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static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
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static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
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static void vlv_prepare_pll(struct intel_crtc *crtc,
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			    const struct intel_crtc_state *pipe_config);
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static void chv_prepare_pll(struct intel_crtc *crtc,
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			    const struct intel_crtc_state *pipe_config);
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static void intel_begin_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
static void intel_finish_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
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static void intel_crtc_init_scalers(struct intel_crtc *crtc,
				    struct intel_crtc_state *crtc_state);
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static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
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static void intel_modeset_setup_hw_state(struct drm_device *dev,
					 struct drm_modeset_acquire_ctx *ctx);
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static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
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struct intel_limit {
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	struct {
		int min, max;
	} dot, vco, n, m, m1, m2, p, p1;

	struct {
		int dot_limit;
		int p2_slow, p2_fast;
	} p2;
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};
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/* returns HPLL frequency in kHz */
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int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
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{
	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };

	/* Obtain SKU information */
	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
		CCK_FUSE_HPLL_FREQ_MASK;

	return vco_freq[hpll_freq] * 1000;
}

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int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
		      const char *name, u32 reg, int ref_freq)
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{
	u32 val;
	int divider;

	val = vlv_cck_read(dev_priv, reg);
	divider = val & CCK_FREQUENCY_VALUES;

	WARN((val & CCK_FREQUENCY_STATUS) !=
	     (divider << CCK_FREQUENCY_STATUS_SHIFT),
	     "%s change in progress\n", name);

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	return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
}

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int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
			   const char *name, u32 reg)
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{
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	int hpll;

	vlv_cck_get(dev_priv);

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	if (dev_priv->hpll_freq == 0)
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		dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
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	hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);

	vlv_cck_put(dev_priv);

	return hpll;
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}

static void intel_update_czclk(struct drm_i915_private *dev_priv)
{
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	if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
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		return;

	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
						      CCK_CZ_CLOCK_CONTROL);

	DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
}

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static inline u32 /* units of 100MHz */
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intel_fdi_link_freq(struct drm_i915_private *dev_priv,
		    const struct intel_crtc_state *pipe_config)
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{
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	if (HAS_DDI(dev_priv))
		return pipe_config->port_clock; /* SPLL */
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	else
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		return dev_priv->fdi_pll_freq;
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}

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static const struct intel_limit intel_limits_i8xx_dac = {
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	.dot = { .min = 25000, .max = 350000 },
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	.vco = { .min = 908000, .max = 1512000 },
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	.n = { .min = 2, .max = 16 },
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	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 2, .max = 33 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 4, .p2_fast = 2 },
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};

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static const struct intel_limit intel_limits_i8xx_dvo = {
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	.dot = { .min = 25000, .max = 350000 },
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	.vco = { .min = 908000, .max = 1512000 },
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	.n = { .min = 2, .max = 16 },
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	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 2, .max = 33 },
	.p2 = { .dot_limit = 165000,
		.p2_slow = 4, .p2_fast = 4 },
};

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static const struct intel_limit intel_limits_i8xx_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
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	.vco = { .min = 908000, .max = 1512000 },
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	.n = { .min = 2, .max = 16 },
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	.m = { .min = 96, .max = 140 },
	.m1 = { .min = 18, .max = 26 },
	.m2 = { .min = 6, .max = 16 },
	.p = { .min = 4, .max = 128 },
	.p1 = { .min = 1, .max = 6 },
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	.p2 = { .dot_limit = 165000,
		.p2_slow = 14, .p2_fast = 7 },
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};
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static const struct intel_limit intel_limits_i9xx_sdvo = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
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	.m1 = { .min = 8, .max = 18 },
	.m2 = { .min = 3, .max = 7 },
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	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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};

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static const struct intel_limit intel_limits_i9xx_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1400000, .max = 2800000 },
	.n = { .min = 1, .max = 6 },
	.m = { .min = 70, .max = 120 },
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	.m1 = { .min = 8, .max = 18 },
	.m2 = { .min = 3, .max = 7 },
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	.p = { .min = 7, .max = 98 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 7 },
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};

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static const struct intel_limit intel_limits_g4x_sdvo = {
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	.dot = { .min = 25000, .max = 270000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 10, .max = 30 },
	.p1 = { .min = 1, .max = 3},
	.p2 = { .dot_limit = 270000,
		.p2_slow = 10,
		.p2_fast = 10
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	},
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};

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static const struct intel_limit intel_limits_g4x_hdmi = {
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	.dot = { .min = 22000, .max = 400000 },
	.vco = { .min = 1750000, .max = 3500000},
	.n = { .min = 1, .max = 4 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 16, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8},
	.p2 = { .dot_limit = 165000,
		.p2_slow = 10, .p2_fast = 5 },
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};

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static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
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	.dot = { .min = 20000, .max = 115000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 14, .p2_fast = 14
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	},
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};

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static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
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	.dot = { .min = 80000, .max = 224000 },
	.vco = { .min = 1750000, .max = 3500000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 104, .max = 138 },
	.m1 = { .min = 17, .max = 23 },
	.m2 = { .min = 5, .max = 11 },
	.p = { .min = 14, .max = 42 },
	.p1 = { .min = 2, .max = 6 },
	.p2 = { .dot_limit = 0,
		.p2_slow = 7, .p2_fast = 7
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	},
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};

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static const struct intel_limit intel_limits_pineview_sdvo = {
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	.dot = { .min = 20000, .max = 400000},
	.vco = { .min = 1700000, .max = 3500000 },
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	/* Pineview's Ncounter is a ring counter */
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	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
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	/* Pineview only has one combined m divider, which we treat as m2. */
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	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 200000,
		.p2_slow = 10, .p2_fast = 5 },
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};

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static const struct intel_limit intel_limits_pineview_lvds = {
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	.dot = { .min = 20000, .max = 400000 },
	.vco = { .min = 1700000, .max = 3500000 },
	.n = { .min = 3, .max = 6 },
	.m = { .min = 2, .max = 256 },
	.m1 = { .min = 0, .max = 0 },
	.m2 = { .min = 0, .max = 254 },
	.p = { .min = 7, .max = 112 },
	.p1 = { .min = 1, .max = 8 },
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	.p2 = { .dot_limit = 112000,
		.p2_slow = 14, .p2_fast = 14 },
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};

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/* Ironlake / Sandybridge
 *
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
 * the range value for them is (actual_value - 2).
 */
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static const struct intel_limit intel_limits_ironlake_dac = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 5 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 5, .max = 80 },
	.p1 = { .min = 1, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 10, .p2_fast = 5 },
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};

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static const struct intel_limit intel_limits_ironlake_single_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 118 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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};

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static const struct intel_limit intel_limits_ironlake_dual_lvds = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 127 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 56 },
	.p1 = { .min = 2, .max = 8 },
	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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};

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/* LVDS 100mhz refclk limits. */
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static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 2 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 28, .max = 112 },
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	.p1 = { .min = 2, .max = 8 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 14, .p2_fast = 14 },
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};

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static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
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	.dot = { .min = 25000, .max = 350000 },
	.vco = { .min = 1760000, .max = 3510000 },
	.n = { .min = 1, .max = 3 },
	.m = { .min = 79, .max = 126 },
	.m1 = { .min = 12, .max = 22 },
	.m2 = { .min = 5, .max = 9 },
	.p = { .min = 14, .max = 42 },
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	.p1 = { .min = 2, .max = 6 },
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	.p2 = { .dot_limit = 225000,
		.p2_slow = 7, .p2_fast = 7 },
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};

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static const struct intel_limit intel_limits_vlv = {
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	 /*
	  * These are the data rate limits (measured in fast clocks)
	  * since those are the strictest limits we have. The fast
	  * clock and actual rate limits are more relaxed, so checking
	  * them would make no difference.
	  */
	.dot = { .min = 25000 * 5, .max = 270000 * 5 },
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Daniel Vetter committed
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	.vco = { .min = 4000000, .max = 6000000 },
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	.n = { .min = 1, .max = 7 },
	.m1 = { .min = 2, .max = 3 },
	.m2 = { .min = 11, .max = 156 },
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	.p1 = { .min = 2, .max = 3 },
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	.p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
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};

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static const struct intel_limit intel_limits_chv = {
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	/*
	 * These are the data rate limits (measured in fast clocks)
	 * since those are the strictest limits we have.  The fast
	 * clock and actual rate limits are more relaxed, so checking
	 * them would make no difference.
	 */
	.dot = { .min = 25000 * 5, .max = 540000 * 5},
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	.vco = { .min = 4800000, .max = 6480000 },
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	.n = { .min = 1, .max = 1 },
	.m1 = { .min = 2, .max = 2 },
	.m2 = { .min = 24 << 22, .max = 175 << 22 },
	.p1 = { .min = 2, .max = 4 },
	.p2 = {	.p2_slow = 1, .p2_fast = 14 },
};

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static const struct intel_limit intel_limits_bxt = {
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	/* FIXME: find real dot limits */
	.dot = { .min = 0, .max = INT_MAX },
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	.vco = { .min = 4800000, .max = 6700000 },
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	.n = { .min = 1, .max = 1 },
	.m1 = { .min = 2, .max = 2 },
	/* FIXME: find real m2 limits */
	.m2 = { .min = 2 << 22, .max = 255 << 22 },
	.p1 = { .min = 2, .max = 4 },
	.p2 = { .p2_slow = 1, .p2_fast = 20 },
};

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/* WA Display #0827: Gen9:all */
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static void
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skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
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{
	if (enable)
		I915_WRITE(CLKGATE_DIS_PSL(pipe),
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			   I915_READ(CLKGATE_DIS_PSL(pipe)) |
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			   DUPS1_GATING_DIS | DUPS2_GATING_DIS);
	else
		I915_WRITE(CLKGATE_DIS_PSL(pipe),
			   I915_READ(CLKGATE_DIS_PSL(pipe)) &
			   ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
}

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/* Wa_2006604312:icl */
static void
icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
		       bool enable)
{
	if (enable)
		I915_WRITE(CLKGATE_DIS_PSL(pipe),
			   I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
	else
		I915_WRITE(CLKGATE_DIS_PSL(pipe),
			   I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
}

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static bool
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needs_modeset(const struct intel_crtc_state *state)
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{
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	return drm_atomic_crtc_needs_modeset(&state->base);
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}

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/*
 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 * The helpers' return value is the rate of the clock that is fed to the
 * display engine's pipe which can be the above fast dot clock rate or a
 * divided-down version of it.
 */
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/* m1 is reserved as 0 in Pineview, n is a ring counter */
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static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
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{
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	clock->m = clock->m2 + 2;
	clock->p = clock->p1 * clock->p2;
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	if (WARN_ON(clock->n == 0 || clock->p == 0))
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		return 0;
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	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
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	return clock->dot;
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}

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static u32 i9xx_dpll_compute_m(struct dpll *dpll)
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{
	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
}

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static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
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{
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	clock->m = i9xx_dpll_compute_m(clock);
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	clock->p = clock->p1 * clock->p2;
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	if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
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		return 0;
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	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
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	return clock->dot;
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}

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static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
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{
	clock->m = clock->m1 * clock->m2;
	clock->p = clock->p1 * clock->p2;
	if (WARN_ON(clock->n == 0 || clock->p == 0))
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		return 0;
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	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
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	return clock->dot / 5;
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}

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int chv_calc_dpll_params(int refclk, struct dpll *clock)
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{
	clock->m = clock->m1 * clock->m2;
	clock->p = clock->p1 * clock->p2;
	if (WARN_ON(clock->n == 0 || clock->p == 0))
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		return 0;
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	clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
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					   clock->n << 22);
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	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
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	return clock->dot / 5;
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}

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#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
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/*
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 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */
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static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
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			       const struct intel_limit *limit,
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			       const struct dpll *clock)
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{
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	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
		INTELPllInvalid("n out of range\n");
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	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
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		INTELPllInvalid("p1 out of range\n");
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	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
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		INTELPllInvalid("m2 out of range\n");
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	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
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		INTELPllInvalid("m1 out of range\n");
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	if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
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	    !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
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		if (clock->m1 <= clock->m2)
			INTELPllInvalid("m1 <= m2\n");

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	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
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	    !IS_GEN9_LP(dev_priv)) {
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		if (clock->p < limit->p.min || limit->p.max < clock->p)
			INTELPllInvalid("p out of range\n");
		if (clock->m < limit->m.min || limit->m.max < clock->m)
			INTELPllInvalid("m out of range\n");
	}

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	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
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		INTELPllInvalid("vco out of range\n");
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	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
	 * connector, etc., rather than just a single range.
	 */
	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
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		INTELPllInvalid("dot out of range\n");
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	return true;
}

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static int
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i9xx_select_p2_div(const struct intel_limit *limit,
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		   const struct intel_crtc_state *crtc_state,
		   int target)
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{
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	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
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	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
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		/*
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		 * For LVDS just rely on its current settings for dual-channel.
		 * We haven't figured out how to reliably set up different
		 * single/dual channel state, if we even can.
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		 */
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		if (intel_is_dual_link_lvds(dev_priv))
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			return limit->p2.p2_fast;
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		else
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			return limit->p2.p2_slow;
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	} else {
		if (target < limit->p2.dot_limit)
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			return limit->p2.p2_slow;
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		else
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			return limit->p2.p2_fast;
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	}
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}

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/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.  The returned values represent the clock equation:
 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 *
 * Target and reference clocks are specified in kHz.
 *
 * If match_clock is provided, then best_clock P divider must match the P
 * divider from @match_clock used for LVDS downclocking.
 */
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static bool
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i9xx_find_best_dpll(const struct intel_limit *limit,
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		    struct intel_crtc_state *crtc_state,
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		    int target, int refclk, struct dpll *match_clock,
		    struct dpll *best_clock)
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{
	struct drm_device *dev = crtc_state->base.crtc->dev;
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	struct dpll clock;
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	int err = target;
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	memset(best_clock, 0, sizeof(*best_clock));
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	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

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	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
	     clock.m1++) {
		for (clock.m2 = limit->m2.min;
		     clock.m2 <= limit->m2.max; clock.m2++) {
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			if (clock.m2 >= clock.m1)
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				break;
			for (clock.n = limit->n.min;
			     clock.n <= limit->n.max; clock.n++) {
				for (clock.p1 = limit->p1.min;
					clock.p1 <= limit->p1.max; clock.p1++) {
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					int this_err;

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					i9xx_calc_dpll_params(refclk, &clock);
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					if (!intel_PLL_is_valid(to_i915(dev),
								limit,
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								&clock))
						continue;
					if (match_clock &&
					    clock.p != match_clock->p)
						continue;

					this_err = abs(clock.dot - target);
					if (this_err < err) {
						*best_clock = clock;
						err = this_err;
					}
				}
			}
		}
	}

	return (err != target);
}

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/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.  The returned values represent the clock equation:
 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 *
 * Target and reference clocks are specified in kHz.
 *
 * If match_clock is provided, then best_clock P divider must match the P
 * divider from @match_clock used for LVDS downclocking.
 */
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static bool
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pnv_find_best_dpll(const struct intel_limit *limit,
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		   struct intel_crtc_state *crtc_state,
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		   int target, int refclk, struct dpll *match_clock,
		   struct dpll *best_clock)
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{
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	struct drm_device *dev = crtc_state->base.crtc->dev;
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	struct dpll clock;
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	int err = target;

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	memset(best_clock, 0, sizeof(*best_clock));
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	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

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	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
	     clock.m1++) {
		for (clock.m2 = limit->m2.min;
		     clock.m2 <= limit->m2.max; clock.m2++) {
			for (clock.n = limit->n.min;
			     clock.n <= limit->n.max; clock.n++) {
				for (clock.p1 = limit->p1.min;
					clock.p1 <= limit->p1.max; clock.p1++) {
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					int this_err;

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					pnv_calc_dpll_params(refclk, &clock);
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					if (!intel_PLL_is_valid(to_i915(dev),
								limit,
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								&clock))
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						continue;
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					if (match_clock &&
					    clock.p != match_clock->p)
						continue;
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					this_err = abs(clock.dot - target);
					if (this_err < err) {
						*best_clock = clock;
						err = this_err;
					}
				}
			}
		}
	}

	return (err != target);
}

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/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.  The returned values represent the clock equation:
 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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 *
 * Target and reference clocks are specified in kHz.
 *
 * If match_clock is provided, then best_clock P divider must match the P
 * divider from @match_clock used for LVDS downclocking.
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 */
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static bool
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g4x_find_best_dpll(const struct intel_limit *limit,
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		   struct intel_crtc_state *crtc_state,
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		   int target, int refclk, struct dpll *match_clock,
		   struct dpll *best_clock)
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{
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	struct drm_device *dev = crtc_state->base.crtc->dev;
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	struct dpll clock;
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	int max_n;
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	bool found = false;
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	/* approximately equals target * 0.00585 */
	int err_most = (target >> 8) + (target >> 9);
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	memset(best_clock, 0, sizeof(*best_clock));
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	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

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	max_n = limit->n.max;
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	/* based on hardware requirement, prefer smaller n to precision */
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	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
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		/* based on hardware requirement, prefere larger m1,m2 */
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		for (clock.m1 = limit->m1.max;
		     clock.m1 >= limit->m1.min; clock.m1--) {
			for (clock.m2 = limit->m2.max;
			     clock.m2 >= limit->m2.min; clock.m2--) {
				for (clock.p1 = limit->p1.max;
				     clock.p1 >= limit->p1.min; clock.p1--) {
					int this_err;

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					i9xx_calc_dpll_params(refclk, &clock);
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					if (!intel_PLL_is_valid(to_i915(dev),
								limit,
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								&clock))
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						continue;
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					this_err = abs(clock.dot - target);
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					if (this_err < err_most) {
						*best_clock = clock;
						err_most = this_err;
						max_n = clock.n;
						found = true;
					}
				}
			}
		}
	}
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	return found;
}

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/*
 * Check if the calculated PLL configuration is more optimal compared to the
 * best configuration and error found so far. Return the calculated error.
 */
static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
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			       const struct dpll *calculated_clock,
			       const struct dpll *best_clock,
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			       unsigned int best_error_ppm,
			       unsigned int *error_ppm)
{
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	/*
	 * For CHV ignore the error and consider only the P value.
	 * Prefer a bigger P value based on HW requirements.
	 */
842
	if (IS_CHERRYVIEW(to_i915(dev))) {
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		*error_ppm = 0;

		return calculated_clock->p > best_clock->p;
	}

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	if (WARN_ON_ONCE(!target_freq))
		return false;

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	*error_ppm = div_u64(1000000ULL *
				abs(target_freq - calculated_clock->dot),
			     target_freq);
	/*
	 * Prefer a better P value over a better (smaller) error if the error
	 * is small. Ensure this preference for future configurations too by
	 * setting the error to 0.
	 */
	if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
		*error_ppm = 0;

		return true;
	}

	return *error_ppm + 10 < best_error_ppm;
}

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/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.  The returned values represent the clock equation:
 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 */
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static bool
874
vlv_find_best_dpll(const struct intel_limit *limit,
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		   struct intel_crtc_state *crtc_state,
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		   int target, int refclk, struct dpll *match_clock,
		   struct dpll *best_clock)
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{
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	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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	struct drm_device *dev = crtc->base.dev;
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	struct dpll clock;
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	unsigned int bestppm = 1000000;
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	/* min update 19.2 MHz */
	int max_n = min(limit->n.max, refclk / 19200);
885
	bool found = false;
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	target *= 5; /* fast clock */

	memset(best_clock, 0, sizeof(*best_clock));
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	/* based on hardware requirement, prefer smaller n to precision */
892
	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
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		for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
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			for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
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			     clock.p2 -= clock.p2 > 10 ? 2 : 1) {
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				clock.p = clock.p1 * clock.p2;
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				/* based on hardware requirement, prefer bigger m1,m2 values */
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				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
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					unsigned int ppm;
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					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
								     refclk * clock.m1);

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					vlv_calc_dpll_params(refclk, &clock);
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					if (!intel_PLL_is_valid(to_i915(dev),
								limit,
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								&clock))
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						continue;

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					if (!vlv_PLL_is_optimal(dev, target,
								&clock,
								best_clock,
								bestppm, &ppm))
						continue;
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					*best_clock = clock;
					bestppm = ppm;
					found = true;
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				}
			}
		}
	}

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	return found;
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}
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/*
 * Returns a set of divisors for the desired target clock with the given
 * refclk, or FALSE.  The returned values represent the clock equation:
 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 */
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static bool
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chv_find_best_dpll(const struct intel_limit *limit,
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		   struct intel_crtc_state *crtc_state,
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		   int target, int refclk, struct dpll *match_clock,
		   struct dpll *best_clock)
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{