intel_dp.c 206 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

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#include <linux/export.h>
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#include <linux/i2c.h>
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#include <linux/notifier.h>
#include <linux/reboot.h>
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#include <linux/slab.h>
#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_hdcp.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/i915_drm.h>
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#include "i915_debugfs.h"
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_atomic.h"
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#include "intel_audio.h"
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#include "intel_connector.h"
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#include "intel_ddi.h"
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#include "intel_display_types.h"
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#include "intel_dp.h"
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#include "intel_dp_link_training.h"
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#include "intel_dp_mst.h"
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#include "intel_dpio_phy.h"
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#include "intel_fifo_underrun.h"
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#include "intel_hdcp.h"
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#include "intel_hdmi.h"
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#include "intel_hotplug.h"
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#include "intel_lspcon.h"
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#include "intel_lvds.h"
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#include "intel_panel.h"
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#include "intel_psr.h"
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#include "intel_sideband.h"
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#include "intel_tc.h"
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#include "intel_vdsc.h"
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#define DP_DPRX_ESI_LEN 14
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/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER	61440

/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE			2720000
#define DP_DSC_MAX_ENC_THROUGHPUT_0		340000
#define DP_DSC_MAX_ENC_THROUGHPUT_1		400000

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/* DP DSC FEC Overhead factor = 1/(0.972261) */
#define DP_DSC_FEC_OVERHEAD_FACTOR		972261
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/* Compliance test status bits  */
#define INTEL_DP_RESOLUTION_SHIFT_MASK	0
#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)

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struct dp_link_dpll {
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	int clock;
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	struct dpll dpll;
};

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static const struct dp_link_dpll g4x_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
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	{ 162000,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ 270000,
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		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
	/*
	 * CHV requires to program fractional division for m2.
	 * m2 is stored in fixed point format using formula below
	 * (m2_int << 22) | m2_fraction
	 */
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	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
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		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
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	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
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		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
};
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/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};

/* With Single pipe configuration, HW is capable of supporting maximum
 * of 4 slices per line.
 */
static const u8 valid_dsc_slicecount[] = {1, 2, 4};

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/**
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 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
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 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
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bool intel_dp_is_edp(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_encoder *encoder,
			       const struct intel_crtc_state *old_crtc_state);
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static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
					   const struct intel_crtc_state *crtc_state);
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static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
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				      enum pipe pipe);
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static void intel_dp_unset_edid(struct intel_dp *intel_dp);
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/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
{
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	static const int dp_rates[] = {
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		162000, 270000, 540000, 810000
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	};
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	int i, max_rate;
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	max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
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	for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
		if (dp_rates[i] > max_rate)
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			break;
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		intel_dp->sink_rates[i] = dp_rates[i];
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	}
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	intel_dp->num_sink_rates = i;
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}

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/* Get length of rates array potentially limited by max_rate. */
static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
{
	int i;

	/* Limit results by potentially reduced max rate */
	for (i = 0; i < len; i++) {
		if (rates[len - i - 1] <= max_rate)
			return len - i;
	}

	return 0;
}

/* Get length of common rates array potentially limited by max_rate. */
static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
					  int max_rate)
{
	return intel_dp_rate_limit_len(intel_dp->common_rates,
				       intel_dp->num_common_rates, max_rate);
}

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/* Theoretical max between source and sink */
static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
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{
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	return intel_dp->common_rates[intel_dp->num_common_rates - 1];
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}

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/* Theoretical max between source and sink */
static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
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{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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	int source_max = intel_dig_port->max_lanes;
	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
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	int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
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	return min3(source_max, sink_max, fia_max);
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}

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int intel_dp_max_lane_count(struct intel_dp *intel_dp)
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{
	return intel_dp->max_link_lane_count;
}

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int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	/* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
	return DIV_ROUND_UP(pixel_clock * bpp, 8);
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}

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int
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intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
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	/* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
	 * link rate that is generally expressed in Gbps. Since, 8 bits of data
	 * is transmitted every LS_Clk per lane, there is no need to account for
	 * the channel encoding that is done in the PHY layer here.
	 */

	return max_link_clock * max_lanes;
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}

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static int
intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	int max_dotclk = dev_priv->max_dotclk_freq;
	int ds_max_dotclk;

	int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;

	if (type != DP_DS_PORT_TYPE_VGA)
		return max_dotclk;

	ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
						    intel_dp->downstream_ports);

	if (ds_max_dotclk != 0)
		max_dotclk = min(max_dotclk, ds_max_dotclk);

	return max_dotclk;
}

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static int cnl_max_source_rate(struct intel_dp *intel_dp)
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{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
	enum port port = dig_port->base.port;

	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;

	/* Low voltage SKUs are limited to max of 5.4G */
	if (voltage == VOLTAGE_INFO_0_85V)
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		return 540000;
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	/* For this SKU 8.1G is supported in all ports */
	if (IS_CNL_WITH_PORT_F(dev_priv))
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		return 810000;
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	/* For other SKUs, max rate on ports A and D is 5.4G */
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	if (port == PORT_A || port == PORT_D)
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		return 540000;
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	return 810000;
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}

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static int icl_max_source_rate(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
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	if (intel_phy_is_combo(dev_priv, phy) &&
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	    !IS_ELKHARTLAKE(dev_priv) &&
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	    !intel_dp_is_edp(intel_dp))
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		return 540000;

	return 810000;
}

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static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
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{
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	/* The values must be in increasing order */
	static const int cnl_rates[] = {
		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
	};
	static const int bxt_rates[] = {
		162000, 216000, 243000, 270000, 324000, 432000, 540000
	};
	static const int skl_rates[] = {
		162000, 216000, 270000, 324000, 432000, 540000
	};
	static const int hsw_rates[] = {
		162000, 270000, 540000
	};
	static const int g4x_rates[] = {
		162000, 270000
	};
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	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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	const struct ddi_vbt_port_info *info =
		&dev_priv->vbt.ddi_port_info[dig_port->base.port];
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	const int *source_rates;
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	int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
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	/* This should only be done once */
	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);

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	if (INTEL_GEN(dev_priv) >= 10) {
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		source_rates = cnl_rates;
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		size = ARRAY_SIZE(cnl_rates);
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		if (IS_GEN(dev_priv, 10))
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			max_rate = cnl_max_source_rate(intel_dp);
		else
			max_rate = icl_max_source_rate(intel_dp);
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	} else if (IS_GEN9_LP(dev_priv)) {
		source_rates = bxt_rates;
		size = ARRAY_SIZE(bxt_rates);
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	} else if (IS_GEN9_BC(dev_priv)) {
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		source_rates = skl_rates;
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		size = ARRAY_SIZE(skl_rates);
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	} else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
		   IS_BROADWELL(dev_priv)) {
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		source_rates = hsw_rates;
		size = ARRAY_SIZE(hsw_rates);
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	} else {
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		source_rates = g4x_rates;
		size = ARRAY_SIZE(g4x_rates);
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	}

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	if (max_rate && vbt_max_rate)
		max_rate = min(max_rate, vbt_max_rate);
	else if (vbt_max_rate)
		max_rate = vbt_max_rate;

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	if (max_rate)
		size = intel_dp_rate_limit_len(source_rates, size, max_rate);

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	intel_dp->source_rates = source_rates;
	intel_dp->num_source_rates = size;
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}

static int intersect_rates(const int *source_rates, int source_len,
			   const int *sink_rates, int sink_len,
			   int *common_rates)
{
	int i = 0, j = 0, k = 0;

	while (i < source_len && j < sink_len) {
		if (source_rates[i] == sink_rates[j]) {
			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
				return k;
			common_rates[k] = source_rates[i];
			++k;
			++i;
			++j;
		} else if (source_rates[i] < sink_rates[j]) {
			++i;
		} else {
			++j;
		}
	}
	return k;
}

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/* return index of rate in rates array, or -1 if not found */
static int intel_dp_rate_index(const int *rates, int len, int rate)
{
	int i;

	for (i = 0; i < len; i++)
		if (rate == rates[i])
			return i;

	return -1;
}

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static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
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{
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	WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
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	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
						     intel_dp->num_source_rates,
						     intel_dp->sink_rates,
						     intel_dp->num_sink_rates,
						     intel_dp->common_rates);

	/* Paranoia, there should always be something in common. */
	if (WARN_ON(intel_dp->num_common_rates == 0)) {
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		intel_dp->common_rates[0] = 162000;
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		intel_dp->num_common_rates = 1;
	}
}

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static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
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				       u8 lane_count)
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{
	/*
	 * FIXME: we need to synchronize the current link parameters with
	 * hardware readout. Currently fast link training doesn't work on
	 * boot-up.
	 */
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	if (link_rate == 0 ||
	    link_rate > intel_dp->max_link_rate)
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		return false;

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	if (lane_count == 0 ||
	    lane_count > intel_dp_max_lane_count(intel_dp))
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		return false;

	return true;
}

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static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
						     int link_rate,
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						     u8 lane_count)
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{
	const struct drm_display_mode *fixed_mode =
		intel_dp->attached_connector->panel.fixed_mode;
	int mode_rate, max_rate;

	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
	max_rate = intel_dp_max_data_rate(link_rate, lane_count);
	if (mode_rate > max_rate)
		return false;

	return true;
}

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int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
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					    int link_rate, u8 lane_count)
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{
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	int index;
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	index = intel_dp_rate_index(intel_dp->common_rates,
				    intel_dp->num_common_rates,
				    link_rate);
	if (index > 0) {
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		if (intel_dp_is_edp(intel_dp) &&
		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
							      intel_dp->common_rates[index - 1],
							      lane_count)) {
			DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
			return 0;
		}
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		intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
		intel_dp->max_link_lane_count = lane_count;
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	} else if (lane_count > 1) {
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		if (intel_dp_is_edp(intel_dp) &&
		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
							      intel_dp_max_common_rate(intel_dp),
							      lane_count >> 1)) {
			DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
			return 0;
		}
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		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
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		intel_dp->max_link_lane_count = lane_count >> 1;
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	} else {
		DRM_ERROR("Link Training Unsuccessful\n");
		return -1;
	}

	return 0;
}

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u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
{
	return div_u64(mul_u32_u32(mode_clock, 1000000U),
		       DP_DSC_FEC_OVERHEAD_FACTOR);
}

static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count,
				       u32 mode_clock, u32 mode_hdisplay)
{
	u32 bits_per_pixel, max_bpp_small_joiner_ram;
	int i;

	/*
	 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
	 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
	 * for SST -> TimeSlotsPerMTP is 1,
	 * for MST -> TimeSlotsPerMTP has to be calculated
	 */
	bits_per_pixel = (link_clock * lane_count * 8) /
			 intel_dp_mode_to_fec_clock(mode_clock);
	DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel);

	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
	max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / mode_hdisplay;
	DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);

	/*
	 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
	 * check, output bpp from small joiner RAM check)
	 */
	bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);

	/* Error out if the max bpp is less than smallest allowed valid bpp */
	if (bits_per_pixel < valid_dsc_bpp[0]) {
		DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
			      bits_per_pixel, valid_dsc_bpp[0]);
		return 0;
	}

	/* Find the nearest match in the array of known BPPs from VESA */
	for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
		if (bits_per_pixel < valid_dsc_bpp[i + 1])
			break;
	}
	bits_per_pixel = valid_dsc_bpp[i];

	/*
	 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
	 * fractional part is 0
	 */
	return bits_per_pixel << 4;
}

static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
				       int mode_clock, int mode_hdisplay)
{
	u8 min_slice_count, i;
	int max_slice_width;

	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
		min_slice_count = DIV_ROUND_UP(mode_clock,
					       DP_DSC_MAX_ENC_THROUGHPUT_0);
	else
		min_slice_count = DIV_ROUND_UP(mode_clock,
					       DP_DSC_MAX_ENC_THROUGHPUT_1);

	max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
	if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
		DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
			      max_slice_width);
		return 0;
	}
	/* Also take into account max slice width */
	min_slice_count = min_t(u8, min_slice_count,
				DIV_ROUND_UP(mode_hdisplay,
					     max_slice_width));

	/* Find the closest match to the valid slice count values */
	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
		if (valid_dsc_slicecount[i] >
		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
						    false))
			break;
		if (min_slice_count  <= valid_dsc_slicecount[i])
			return valid_dsc_slicecount[i];
	}

	DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
	return 0;
}

586
static enum drm_mode_status
587
588
589
intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
590
	struct intel_dp *intel_dp = intel_attached_dp(connector);
591
592
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
593
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
594
595
	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
596
	int max_dotclk;
597
598
	u16 dsc_max_output_bpp = 0;
	u8 dsc_slice_count = 0;
599

600
601
602
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

603
	max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
604

605
	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
606
		if (mode->hdisplay > fixed_mode->hdisplay)
607
608
			return MODE_PANEL;

609
		if (mode->vdisplay > fixed_mode->vdisplay)
610
			return MODE_PANEL;
611
612

		target_clock = fixed_mode->clock;
613
614
	}

615
	max_link_clock = intel_dp_max_link_rate(intel_dp);
616
	max_lanes = intel_dp_max_lane_count(intel_dp);
617
618
619
620

	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

621
622
623
624
625
626
627
628
629
630
631
632
	/*
	 * Output bpp is stored in 6.4 format so right shift by 4 to get the
	 * integer value since we support only integer values of bpp.
	 */
	if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
	    drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
		if (intel_dp_is_edp(intel_dp)) {
			dsc_max_output_bpp =
				drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
			dsc_slice_count =
				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
								true);
633
		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
634
635
636
637
638
639
640
641
642
643
644
645
646
647
			dsc_max_output_bpp =
				intel_dp_dsc_get_output_bpp(max_link_clock,
							    max_lanes,
							    target_clock,
							    mode->hdisplay) >> 4;
			dsc_slice_count =
				intel_dp_dsc_get_slice_count(intel_dp,
							     target_clock,
							     mode->hdisplay);
		}
	}

	if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
	    target_clock > max_dotclk)
648
		return MODE_CLOCK_HIGH;
649
650
651
652

	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

653
654
655
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

656
	return intel_mode_valid_max_plane_size(dev_priv, mode);
657
658
}

659
u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
660
{
661
662
	int i;
	u32 v = 0;
663
664
665
666

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
667
		v |= ((u32)src[i]) << ((3 - i) * 8);
668
669
670
	return v;
}

671
static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
672
673
674
675
676
677
678
679
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

680
static void
681
intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
682
static void
683
intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
684
					      bool force_disable_vdd);
685
static void
686
intel_dp_pps_init(struct intel_dp *intel_dp);
687

688
689
static intel_wakeref_t
pps_lock(struct intel_dp *intel_dp)
690
{
691
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
692
	intel_wakeref_t wakeref;
693
694

	/*
695
	 * See intel_power_sequencer_reset() why we need
696
697
	 * a power domain reference here.
	 */
698
699
	wakeref = intel_display_power_get(dev_priv,
					  intel_aux_power_domain(dp_to_dig_port(intel_dp)));
700
701

	mutex_lock(&dev_priv->pps_mutex);
702
703

	return wakeref;
704
705
}

706
707
static intel_wakeref_t
pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
708
{
709
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
710
711

	mutex_unlock(&dev_priv->pps_mutex);
712
713
714
715
	intel_display_power_put(dev_priv,
				intel_aux_power_domain(dp_to_dig_port(intel_dp)),
				wakeref);
	return 0;
716
717
}

718
719
720
#define with_pps_lock(dp, wf) \
	for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))

721
722
723
static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
724
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
725
726
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum pipe pipe = intel_dp->pps_pipe;
727
728
729
	bool pll_enabled, release_cl_override = false;
	enum dpio_phy phy = DPIO_PHY(pipe);
	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
730
	u32 DP;
731
732

	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
733
734
735
		 "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
		 pipe_name(pipe), intel_dig_port->base.base.base.id,
		 intel_dig_port->base.base.name))
736
737
		return;

738
739
740
	DRM_DEBUG_KMS("kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
		      pipe_name(pipe), intel_dig_port->base.base.base.id,
		      intel_dig_port->base.base.name);
741
742
743
744
745
746
747
748
749

	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
	DP |= DP_PORT_WIDTH(1);
	DP |= DP_LINK_TRAIN_PAT_1;

750
	if (IS_CHERRYVIEW(dev_priv))
751
752
753
		DP |= DP_PIPE_SEL_CHV(pipe);
	else
		DP |= DP_PIPE_SEL(pipe);
754

755
756
757
758
759
760
	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;

	/*
	 * The DPLL for the pipe must be enabled for this to work.
	 * So enable temporarily it if it's not already enabled.
	 */
761
	if (!pll_enabled) {
762
		release_cl_override = IS_CHERRYVIEW(dev_priv) &&
763
764
			!chv_phy_powergate_ch(dev_priv, phy, ch, true);

765
		if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
766
767
768
769
770
				     &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
			DRM_ERROR("Failed to force on pll for pipe %c!\n",
				  pipe_name(pipe));
			return;
		}
771
	}
772

773
774
775
	/*
	 * Similar magic as in intel_dp_enable_port().
	 * We _must_ do this port enable + disable trick
776
	 * to make this power sequencer lock onto the port.
777
778
779
780
781
782
783
784
785
786
	 * Otherwise even VDD force bit won't work.
	 */
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
787

788
	if (!pll_enabled) {
789
		vlv_force_pll_off(dev_priv, pipe);
790
791
792
793

		if (release_cl_override)
			chv_phy_powergate_ch(dev_priv, phy, ch, false);
	}
794
795
}

796
797
798
799
800
801
802
803
804
static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
{
	struct intel_encoder *encoder;
	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);

	/*
	 * We don't have power sequencer currently.
	 * Pick one that's not used by other ports.
	 */
805
806
	for_each_intel_dp(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827

		if (encoder->type == INTEL_OUTPUT_EDP) {
			WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
				intel_dp->active_pipe != intel_dp->pps_pipe);

			if (intel_dp->pps_pipe != INVALID_PIPE)
				pipes &= ~(1 << intel_dp->pps_pipe);
		} else {
			WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);

			if (intel_dp->active_pipe != INVALID_PIPE)
				pipes &= ~(1 << intel_dp->active_pipe);
		}
	}

	if (pipes == 0)
		return INVALID_PIPE;

	return ffs(pipes) - 1;
}

828
829
830
static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
831
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
832
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
833
	enum pipe pipe;
834

835
	lockdep_assert_held(&dev_priv->pps_mutex);
836

837
	/* We should never land here with regular DP ports */
838
	WARN_ON(!intel_dp_is_edp(intel_dp));
839

840
841
842
	WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
		intel_dp->active_pipe != intel_dp->pps_pipe);

843
844
845
	if (intel_dp->pps_pipe != INVALID_PIPE)
		return intel_dp->pps_pipe;

846
	pipe = vlv_find_free_pps(dev_priv);
847
848
849
850
851

	/*
	 * Didn't find one. This should not happen since there
	 * are two power sequencers and up to two eDP ports.
	 */
852
	if (WARN_ON(pipe == INVALID_PIPE))
853
		pipe = PIPE_A;
854

855
	vlv_steal_power_sequencer(dev_priv, pipe);
856
	intel_dp->pps_pipe = pipe;
857

858
	DRM_DEBUG_KMS("picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
859
		      pipe_name(intel_dp->pps_pipe),
860
861
		      intel_dig_port->base.base.base.id,
		      intel_dig_port->base.base.name);
862
863

	/* init power sequencer on this pipe and port */
864
865
	intel_dp_init_panel_power_sequencer(intel_dp);
	intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
866

867
868
869
870
871
	/*
	 * Even vdd force doesn't work until we've made
	 * the power sequencer lock in on the port.
	 */
	vlv_power_sequencer_kick(intel_dp);
872
873
874
875

	return intel_dp->pps_pipe;
}

876
877
878
static int
bxt_power_sequencer_idx(struct intel_dp *intel_dp)
{
879
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
880
	int backlight_controller = dev_priv->vbt.backlight.controller;
881
882
883
884

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* We should never land here with regular DP ports */
885
	WARN_ON(!intel_dp_is_edp(intel_dp));
886
887

	if (!intel_dp->pps_reset)
888
		return backlight_controller;
889
890
891
892
893
894
895

	intel_dp->pps_reset = false;

	/*
	 * Only the HW needs to be reprogrammed, the SW state is fixed and
	 * has been setup during connector init.
	 */
896
	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
897

898
	return backlight_controller;
899
900
}

901
902
903
904
905
906
typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
			       enum pipe pipe);

static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
907
	return I915_READ(PP_STATUS(pipe)) & PP_ON;
908
909
910
911
912
}

static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
				enum pipe pipe)
{
913
	return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
914
915
916
917
918
919
920
}

static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
			 enum pipe pipe)
{
	return true;
}
921

922
static enum pipe
923
924
925
vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
		     enum port port,
		     vlv_pipe_check pipe_check)
926
927
{
	enum pipe pipe;
928
929

	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
930
		u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
931
			PANEL_PORT_SELECT_MASK;
932
933
934
935

		if (port_sel != PANEL_PORT_SELECT_VLV(port))
			continue;

936
937
938
		if (!pipe_check(dev_priv, pipe))
			continue;

939
		return pipe;
940
941
	}

942
943
944
945
946
947
	return INVALID_PIPE;
}

static void
vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
{
948
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
949
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
950
	enum port port = intel_dig_port->base.port;
951
952
953
954

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* try to find a pipe with this port selected */
955
956
957
958
959
960
961
962
963
964
965
	/* first pick one where the panel is on */
	intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
						  vlv_pipe_has_pp_on);
	/* didn't find one? pick one where vdd is on */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_has_vdd_on);
	/* didn't find one? pick one with just the correct port */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_any);
966
967
968

	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
	if (intel_dp->pps_pipe == INVALID_PIPE) {
969
970
971
		DRM_DEBUG_KMS("no initial power sequencer for [ENCODER:%d:%s]\n",
			      intel_dig_port->base.base.base.id,
			      intel_dig_port->base.base.name);
972
		return;
973
974
	}

975
976
977
978
	DRM_DEBUG_KMS("initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
		      intel_dig_port->base.base.base.id,
		      intel_dig_port->base.base.name,
		      pipe_name(intel_dp->pps_pipe));
979

980
981
	intel_dp_init_panel_power_sequencer(intel_dp);
	intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
982
983
}

984
void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
985
986
987
{
	struct intel_encoder *encoder;

988
	if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
989
		    !IS_GEN9_LP(dev_priv)))
990
991
992
993
994
995
996
997
998
999
1000
1001
		return;

	/*
	 * We can't grab pps_mutex here due to deadlock with power_domain
	 * mutex when power_domain functions are called while holding pps_mutex.
	 * That also means that in order to use pps_pipe the code needs to
	 * hold both a power domain reference and pps_mutex, and the power domain
	 * reference get/put must be done while _not_ holding pps_mutex.
	 * pps_{lock,unlock}() do these steps in the correct order, so one
	 * should use them always.
	 */

1002
1003
	for_each_intel_dp(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1004

1005
1006
1007
1008
1009
		WARN_ON(intel_dp->active_pipe != INVALID_PIPE);

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

1010
		if (IS_GEN9_LP(dev_priv))
1011
1012
1013
			intel_dp->pps_reset = true;
		else
			intel_dp->pps_pipe = INVALID_PIPE;
1014
	}
1015
1016
}

1017
1018
1019
1020
1021
1022
1023
1024
struct pps_registers {
	i915_reg_t pp_ctrl;
	i915_reg_t pp_stat;
	i915_reg_t pp_on;
	i915_reg_t pp_off;
	i915_reg_t pp_div;
};

1025
static void intel_pps_get_registers(struct intel_dp *intel_dp,
1026
1027
				    struct pps_registers *regs)
{
1028
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1029
1030
	int pps_idx = 0;

1031
1032
	memset(regs, 0, sizeof(*regs));

1033
	if (IS_GEN9_LP(dev_priv))
1034
1035
1036
		pps_idx = bxt_power_sequencer_idx(intel_dp);
	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
		pps_idx = vlv_power_sequencer_pipe(intel_dp);
1037

1038
1039
1040
1041
	regs->pp_ctrl = PP_CONTROL(pps_idx);
	regs->pp_stat = PP_STATUS(pps_idx);
	regs->pp_on = PP_ON_DELAYS(pps_idx);
	regs->pp_off = PP_OFF_DELAYS(pps_idx);
1042
1043

	/* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1044
	if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1045
1046
		regs->pp_div = INVALID_MMIO_REG;
	else
1047
		regs->pp_div = PP_DIVISOR(pps_idx);
1048
1049
}

1050
1051
static i915_reg_t
_pp_ctrl_reg(struct intel_dp *intel_dp)
1052
{
1053
	struct pps_registers regs;
1054

1055
	intel_pps_get_registers(intel_dp, &regs);
1056
1057

	return regs.pp_ctrl;
1058
1059
}

1060
1061
static i915_reg_t
_pp_stat_reg(struct intel_dp *intel_dp)
1062
{
1063
	struct pps_registers regs;
1064