• Maarten Lankhorst's avatar
    drm/i915/dp: Fix dsc bpp calculations, v5. · ed06efb8
    Maarten Lankhorst authored
    
    
    There was a integer wraparound when mode_clock became too high,
    and we didn't correct for the FEC overhead factor when dividing,
    with the calculations breaking at HBR3.
    
    As a result our calculated bpp was way too high, and the link width
    limitation never came into effect.
    
    Print out the resulting bpp calcululations as a sanity check, just
    in case we ever have to debug it later on again.
    
    We also used the wrong factor for FEC. While bspec mentions 2.4%,
    all the calculations use 1/0.972261, and the same ratio should be
    applied to data M/N as well, so use it there when FEC is enabled.
    
    This fixes the FIFO underrun we are seeing with FEC enabled.
    
    Changes since v2:
    - Handle fec_enable in intel_link_compute_m_n, so only data M/N is adjusted. (Ville)
    - Fix initial hardware readout for FEC. (Ville)
    Changes since v3:
    - Remove bogus fec_to_mode_clock. (Ville)
    Changes since v4:
    - Use the correct register for icl. (Ville)
    - Split hw readout to a separate patch.
    Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
    Fixes: d9218c8f ("drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC")
    Cc: <stable@vger.kernel.org> # v5.0+
    Cc: Manasi Navare <manasi.d.navare@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190925082110.17439-1-maarten.lankhorst@linux.intel.com
    
    Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    ed06efb8