- 25 Sep, 2019 1 commit
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Maarten Lankhorst authored
There was a integer wraparound when mode_clock became too high, and we didn't correct for the FEC overhead factor when dividing, with the calculations breaking at HBR3. As a result our calculated bpp was way too high, and the link width limitation never came into effect. Print out the resulting bpp calcululations as a sanity check, just in case we ever have to debug it later on again. We also used the wrong factor for FEC. While bspec mentions 2.4%, all the calculations use 1/0.972261, and the same ratio should be applied to data M/N as well, so use it there when FEC is enabled. This fixes the FIFO underrun we are seeing with FEC enabled. Changes since v2: - Handle fec_enable in intel_link_compute_m_n, so only data M/N is adjusted. (Ville) - Fix initial hardware readout for FEC. (Ville) Changes since v3: - Remove bogus fec_to_mode_clock. (Ville) Changes since v4: - Use the correct register for icl. (Ville) - Split hw readout to a separate patch. Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes: d9218c8f ("drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC") Cc: <stable@vger.kernel.org> # v5.0+ Cc: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190925082110.17439-1-maarten.lankhorst@linux.intel.com Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com>
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- 23 Sep, 2019 2 commits
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Jani Nikula authored
In general, prefer struct drm_i915_private * over struct drm_device * when either will do. Rename the local variables to i915. No functional changes. Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190920185421.17822-6-jani.nikula@intel.com
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Jani Nikula authored
In general, prefer struct drm_i915_private * over struct drm_device * when either will do. Rename the local variable to i915. Also propagate to intel_hpd_poll_fini(). No functional changes. Reviewed-by:
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- 19 Sep, 2019 1 commit
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Ville Syrjälä authored
Modern platforms allow the transcoders hdisplay/vdisplay to exceed the planes' max resolution. This has the nasty implication that modes on the connectors' mode list may not be usable when the user asks for a fullscreen plane. Seeing as that is the most common use case it seems prudent to filter out modes that don't allow for fullscreen planes to be enabled. Let's do that in the connetor .mode_valid() hook so that normally such modes are kept hidden but the user is still able to forcibly specify such a mode if they know they don't need fullscreen planes. This is in line with ealier policies regarding certain clock limits. The idea is to prevent the casual user from encountering a mode that would fail under typical conditions, but allow the expert user to force things if they so wish. Maybe in the future we should consider automagically using two planes when one can't cover the entire screen? Wouldn't be a great match for the current uapi with explicit planes though, but I guess no worse than using two pipes (which we apparently have to in the future anyway). Either that or we'd have to teach userspace to do it for us. v2: Fix icl+ max plane heigth (Manasi) Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Leho Kraav <leho@kraav.com> Cc: Sean Paul <sean@poorly.run> Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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- 16 Sep, 2019 1 commit
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Ville Syrjälä authored
There's a helper in drm_fourcc.h these days to check of we're dealing with a two plane YUV format. Make use if it. Also s/plane/color_plane/ in skl_plane_relative_data_rate() to reduce the confusion. Reviewed-by:
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- 11 Sep, 2019 1 commit
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Jani Nikula authored
Abstract away direct access to ->num_pipes to allow further refactoring. No functional changes. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Acked-by:
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- 30 Aug, 2019 1 commit
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Ramalingam C authored
We dont need the definition of the enum port outside I915, anymore. Hence move enum port definition into I915 driver itself. v2: intel_display.h is included in intel_hdcp.h v3: enum port is declared in headers. v4: commit msg is rephrased. v5: copyright year is updated [Tomas] Signed-off-by:
Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Shashank Sharma <shashank.sharma@intel.com> Reviewed-by:
Tomas Winkler <tomas.winkler@intel.com> Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190828164216.405-3-ramalingam.c@intel.com
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- 27 Aug, 2019 1 commit
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José Roberto de Souza authored
Same as for_each_oldnew_intel_crtc_in_state() but iterates in reverse order. v2: Fix additional blank line v3: Rebase Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190823082055.5992-12-lucas.demarchi@intel.com
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- 09 Aug, 2019 1 commit
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Jani Nikula authored
It's for display. Seems like a better fit. Reduce clutter in i915_drv.h. Reviewed-by:
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- 07 Aug, 2019 1 commit
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Jani Nikula authored
Move the declarations of functions in intel_display.c to intel_display.h. There is still plenty of cleanup to do in intel_display.[ch], but one step at a time. Reviewed-by:
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- 12 Jul, 2019 1 commit
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Anusha Srivatsa authored
Some platforms may have Modular FIA. If Modular FIA is used in the SOC, then Display Driver will access the additional instances of FIA based on pre-assigned offset in GTTMADDR space. Each Modular FIA instance has its own IOSF Sideband Port ID and it houses only 2 Type-C Port. In SOC that has more than two Type-C Ports, there are multiple instances of Modular FIA. Gunit will need to use different destination ID when it access different pair of Type-C Port. The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If Modular FIA is used in the SOC, this register bit exists in all the instances of Modular FIA. IOM FW is required to program only the MF bit in first FIA instance that houses the Type-C Port 0 and Port 1, for Display Driver to read from. v2 (Lucas): - Move all accesses to FIA to be contained in intel_tc.c, along with display_fia that is now called tc_phy_fia - Save the fia instance number on intel_digital_port, so we don't have to query if modular FIA is used on every access v3 (Lucas): Make function static v4 (Lucas): Move enum phy_fia to the header and use it in intel_digital_port (suggested by Ville) v5 (Lucas): Add comment about the mapping between FIA and TC port (suggested by Stuart) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
Stuart Summers <stuart.summers@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190712055706.12143-2-lucas.demarchi@intel.com
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- 11 Jul, 2019 6 commits
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Mahesh Kumar authored
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are mapped to TC ports. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by:
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Lucas De Marchi authored
Tiger Lake has up to 3 combo phys and 6 TC phys. Extend the helper conversion functions from port to phy. Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-14-lucas.demarchi@intel.com
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Vandita Kulkarni authored
There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a combophy port. This results in 6 typeC ports and 3 combophy ports. These 6 TC ports can be DP alternate mode, DP over thunderbolt, native DP on legacy DP connector or native HDMI on legacy connector. v2: Rebase on new modular FIA code (Lucas) v3: Also add new port in port_identifier(), even though it can't possibly be used there (requested by José) v4: Add conversion port->tc_port in helper function after introction of phy namespace (Lucas) Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by:
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Lucas De Marchi authored
Add pipe D and transcoder D to prepare for platforms having them. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Matt Roper authored
Convert the code that operates directly on gen11 combo PHY's to use the new namespace. Combo PHY registers are those named "ICL_PORT_*" plus ICL_DPHY_CHKN. Note that a lot of the PHY programming happens in the MIPI DSI code. For clarity I've added a for_each_dsi_phy() to loop over the phys used by DSI. Since DSI always uses A & B on gen11, port=phy in all cases so it doesn't actually matter which form we use in the DSI code. I've used the phy iterator in code that's explicitly working with the combo PHY, but left the rest of the DSI code using the port iterator and namespace to minimize patch deltas. We can switch the rest of the DSI code over to use phy terminology later if this winds up being too confusing. v6: Drop an include of drm/i915_drm.h; that was previously included just for the definition of 'enum port' which this patch removes the need for. (Jose) Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: -
Matt Roper authored
Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping. Because of this, both the bspec documentation and our i915 code has used the term "port" when talking about either DDI's or PHY's; it was always easy to tell what terms like "Port A" were referring to from the context. Unfortunately this is starting to break down now that EHL allows PHY-A to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving PHY-A considered "Port A" or "Port D?" The answer depends on which register we're working with, and even the bspec doesn't do a great job of clarifying this. Let's try to be more explicit about whether we're talking about the DDI or the PHY on gen11+ by using 'port' to refer to the DDI and creating a new 'enum phy' namespace to refer to the PHY in use. This patch just adds the new PHY namespace, new phy-based versions of intel_port_is_*(), and a helper to convert a port to a PHY. Transitioning various areas of the code over to using the PHY namespace will be done in subsequent patches to make review easier. We'll remove the intel_port_is_*() functions at the end of the series when we transition all callers over to using the PHY-based versions. v2: - Convert a few more 'port' uses to 'phy.' (Sparse) v3: - Switch DDI_CLK_SEL() back to 'port.' (Jose) - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY for its bit definitions, even though the register description is given in terms of DDI. - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using port and create separate ICL+ definitions that work in terms of PHY. v4: - Rebase and resolve conflicts with Imre's TC series. - This patch now just adds the namespace and a few convenience functions; the important changes are now split out into separate patches to make review easier. Suggested-by:
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- 01 Jul, 2019 1 commit
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Imre Deak authored
The TypeC port mode can switch dynamically, to reflect that better call the port's mode as 'mode' rather than 'type'. While at it: - s/TC_PORT_TBT/TC_PORT_TBT_ALT/ and s/TC_PORT_TYPEC/TC_PORT_DP_ALT/. 'TYPEC' is ambiguous, TBT_ALT and DP_ALT better match the reality. - Remove the 'unknown' TypeC port mode. The mode is always known, it's the TBT-alt/safe mode after HW reset and after disconnecting the PHY. Simplify the tc_port/tc_type checks accordingly. - Don't WARN if the port mode changes, that can happen normally. No functional changes. Cc: Animesh Manna <animesh.manna@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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- 17 Jun, 2019 1 commit
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Jani Nikula authored
Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by:
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- 04 Jun, 2019 1 commit
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Daniele Ceraolo Spurio authored
Move over structures, enums and macros from intel_display.h and i915_drv.h to have all the display PM defines in the same header. Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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- 20 May, 2019 2 commits
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Ville Syrjälä authored
Align dumb buffer stride to 4k if the fb will be big enough to require gtt remapping. v2: Leave the stride alone for buffers that look to be for the cursor v3: Make it not a hack (Daniel) Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by:
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Ville Syrjälä authored
The display engine stride limits are getting in our way. On SKL+ we are limited to 8k pixels, which is easily exceeded with three 4k displays. To overcome this limitation we can remap the pages in the GTT to provide the display engine with a view of memory with a smaller stride. The code is mostly already there as We already play tricks with the plane surface address and x/y offsets. A few caveats apply: * linear buffers need the fb stride to be page aligned, as otherwise the remapped lines wouldn't start at the same spot * compressed buffers can't be remapped due to the new ccs hash mode causing the virtual address of the pages to affect the interpretation of the compressed data. IIRC the old hash was limited to the low 12 bits so if we were using that mode we could remap. As it stands we just refuse to remapp with compressed fbs. * no remapping gen2/3 as we'd need a fence for the remapped vma, which we currently don't have. Need to deal with the fence POT requirements, and do something about the gen2 gtt page size vs tile size difference v2: Rebase due to is_ccs_modifier() Fix up the skl+ stride_mult mess memset() the gtt_view because otherwise we could leave junk in plane[1] when going from 2 plane to 1 plane format v3: intel_check_plane_stride() was split out v4: Drop the aligned viewport stuff, it was meant for ccs which can't be remapped anyway v5: Introduce intel_plane_can_remap() Reorder the code so that plane_state->view gets filled even for invisible planes, otherwise we'd keep using stale values and could explode during remapping. The new logic never remaps invisible planes since we don't have a viewport, and instead pins the full fb instead v6: Fix plane src coord checks after remapping by moving plane_state->base.src to the final plane x/y offsets. Allow intel_plane_check_stride() to fail even with remapping (can happen at least with a linear 64bpp fb with a 4k plane and a suitably inconvenient src coordinates). Improve aux plane FIXME (Daniel) Move some code shuffling into a separate patch (Daniel) Testcase: igt/kms_big_fb Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
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- 14 May, 2019 2 commits
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Imre Deak authored
There isn't a separate power domain specific to PLLs. When programming them we require the same power domain to be enabled which is needed when accessing other display core parts (not specific to any pipe/port/transcoder). This corresponds to the DISPLAY_CORE domain added previously in this patchset, so use that instead to save bits in the power domain mask. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Signed-off-by:
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Imre Deak authored
We don't need the AUX power for the whole duration of the detect, only when we're doing AUX transfers. The AUX transfer function takes its own reference on the AUX power domain already. The two places during detect which access display core registers (not specific to a pipe/port/transcoder) only need the power domain that is required for that access. That power domain is equivalent to the device global power domain on most platforms (enabled whenever we hold a runtime PM reference) except on CHV/VLV where it's equivalent to the display power well. Add a new power domain that reflects the above, and use this at the two spots accessing registers. With that we can avoid taking the AUX reference for the whole duration of the detect function. Put the domains asynchronously to avoid the unneeded on-off-on toggling. Also adapt the idea from with_intel_runtime_pm et al. for making it easy to write short sequences where a display power ref is needed. v2: (Ville) - Add with_intel_display_power() helper to simplify things. - s/bool res/bool is_connected/ Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Signed-off-by:
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- 06 May, 2019 1 commit
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Ville Syrjälä authored
hsw_enable_pc8()/hsw_disable_pc8() are more less equivalent to the display core init/unit functions of later platforms. Relocate the hsw/bdw code into intel_runtime_pm.c so that it sits next to its cousins. Signed-off-by:
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- 15 Feb, 2019 1 commit
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Ramalingam C authored
For the reusability of the enum port in other driver modules (like mei_hdcp), enum port definition is moved from I915 local header intel_display.h to drm/i915_drm.h Signed-off-by:
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- 02 Jan, 2019 1 commit
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Jani Nikula authored
First move the low hanging fruit, the fields that are only initialized runtime. Use RUNTIME_INFO() exclusively to access the fields. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
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- 29 Nov, 2018 2 commits
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Manasi Navare authored
On Icelake, a separate power well PG2 is created for VDSC engine used for eDP/MIPI DSI. This patch adds a new display power domain for Power well 2. v3: * Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville) * Move it around TRANSCODER power domain defs (Ville) v2: * Fix the power well mismatch CI error (Ville) * Rename as VDSC_PIPE_A (Imre) * Fix a whitespace (Anusha) * Fix Comments (Imre) Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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Manasi Navare authored
DSC params like the enable, compressed bpp, slice count and dsc_split are added to the intel_crtc_state. These parameters are set based on the requested mode and available link parameters during the pipe configuration in atomic check phase. These values are then later used to populate the remaining DSC and RC parameters before enbaling DSC in atomic commit. v15: * Rebase over drm-tip v14: Remove leftovers, use dsc_bpc, refine dsc_compute_config (Ville) v13: * Compute DSC bpc only when DSC is req to be enabled (Ville) v12: * Override bpp with dsc dpcd color depth (Manasi) v11: * Const crtc_state, reject DSC on DP without FEC (Ville) * Dont set dsc_split to false (Ville) v10: * Add a helper for dp_dsc support (Ville) * Set pipe_config to max bpp, link params for DSC for now (Ville) * Compute bpp - use dp dsc support helper (Ville) v9: * Rebase on top of drm-tip that now uses fast_narrow config for edp (Manasi) v8: * Check for DSC bpc not 0 (manasi) v7: * Fix indentation in compute_m_n (Manasi) v6 (From Gaurav): * Remove function call of intel_dp_compute_dsc_params() and invoke intel_dp_compute_dsc_params() in the patch where it is defined to fix compilation warning (Gaurav) v5: Add drm_dsc_cfg in intel_crtc_state (Manasi) v4: * Rebase on refactoring of intel_dp_compute_config on tip (Manasi) * Add a comment why we need to check PSR while enabling DSC (Gaurav) v3: * Check PPR > max_cdclock to use 2 VDSC instances (Ville) v2: * Add if-else for eDP/DP (Gaurav) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181128213621.21391-1-manasi.d.navare@intel.com
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- 28 Nov, 2018 2 commits
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Ville Syrjälä authored
On SKL+ the plane WM/BUF_CFG registers are a proper part of each plane's register set. That means accessing them will cancel any pending plane update, and we would need a PLANE_SURF register write to arm the wm/ddb change as well. To avoid all the problems with that let's just move the wm/ddb programming into the plane update/disable hooks. Now all plane registers get written in one (hopefully atomic) operation. To make that feasible we'll move the plane ddb tracking into the crtc state. Watermarks were already tracked there. v2: Rebase due to input CSC v3: Split out a bunch of junk (Matt) v4: Add skl_wm_add_affected_planes() to deal with cursor special case and non-zero wm register reset value v5: Drop the unrelated for_each_intel_plane_mask() fix (Matt) Remove the redundant ddb memset() (Matt) Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #v3 Signed-off-by: -
Ville Syrjälä authored
We're going to need access to the new crtc state in ->disable_plane() for SKL+ wm/ddb programming and pre-skl pipe gamma/csc control. Pass the crtc state down. We'll also try to make intel_crtc_disable_planes() do the right thing as much as it's possible. The fact that we don't have a separate crtc state for the disabled state when we're going to re-enable the crtc later means we might end up poking at a few extra planes in there. But that's harmless. I suppose one might argue that we wouldn't have to care about proper ddb/wm/csc/gamma if the pipe is going to permanently disable anyway, but the state checker probably cares so we should try our best to make sure everything is programmed correctly even in that case. v2: Fix the commit message a bit (Matt) Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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- 21 Nov, 2018 1 commit
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Imre Deak authored
Add a comment to the pipe and transcoder enum definitions about our assumption in the code about enum values for pipes and transcoders with a 1:1 transcoder -> pipe mapping. v2: - Clarify more what are the assumptions about the enum values. (Ville) v3: (Lucas) - s/->/ -> / so it looks less like pointer dereferencing. - Use pipe enums as initializers in the transcoder enum definition. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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- 16 Nov, 2018 1 commit
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Lucas De Marchi authored
Do like it's done for list.h macros, and use "reverse" suffix rather than "rev". Signed-off-by:
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- 24 Oct, 2018 1 commit
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Maarten Lankhorst authored
Gen11 supports 7 planes + 1 cursor on each pipe. Bump I915_MAX_PLANES to 8, and set num_sprites correctly. Signed-off-by:
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- 22 Oct, 2018 1 commit
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Madhav Chauhan authored
This patch adds a helper function to retrieve DSI transcoder for a given DSI port using newly defined enum names for DSI transcoders. Signed-off-by:
Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by:
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- 19 Sep, 2018 1 commit
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Lee, Shawn C authored
Some DP dongles in particular seem to be fussy about too large link M/N values. Set specific value for N divider can resolve this issue per dongle vendor's comment. So configure N as constant value (0x8000) to instead of reduce M/N formula when specific DP dongle connected. v2: add more comments for issue description and fix typo. v3: add lost commit messages back for version 2 v4: send patch to both intel-gfx and dri-devel Cc: Jani Nikula <jani.nikula@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Tested-by:
Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
Lee, Shawn C <shawn.c.lee@intel.com> Signed-off-by:
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- 09 Sep, 2018 1 commit
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Daniel Vetter authored
We have a bunch of neat little macros all over the place which should move to kernel.h. But some of them died in bikesheds on lkml, and we need a decent home for them. Start out by moving the for_each_if macro there. v2: Rename to drm_util.h instead (Dave&Sean) Cc: Sean Paul <seanpaul@chromium.org> Acked-by:
Sean Paul <seanpaul@chromium.org> Cc: Dave Airlie <airlied@gmail.com> Acked-by:
Dave Airlie <airlied@gmail.com> Signed-off-by:
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- 22 Aug, 2018 1 commit
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Dhinakaran Pandiyan authored
Code looks cleaner with modifiers hidden inside this wrapper. v2: Remove const qualifier (Ville) Signed-off-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by:
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- 16 Aug, 2018 1 commit
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Lucas De Marchi authored
Instead of defining all registers twice, define just a PCH_GPIO_BASE that has the same address as PCH_GPIO_A and use that to calculate all the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing the same thing. v2: Fix GMBUS registers to be relative to gpio base; create GPIO() macro to return a particular gpio address and move the enum out of i915_reg.h (suggested by Jani) v3: Move base offset inside the GPIO() macro so the GMBUS defines don't actually need to be changed (suggested by Daniel/Ville) v4: Move definition of i915_gpio to intel_display.h and remove GMBUS/GPIO handling from gvt since now they have their own defines. Signed-off-by:
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- 08 Aug, 2018 1 commit
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Imre Deak authored
It makes sense to keep unchanging data const. Extract such fields from the i915_power_well struct into a new i915_power_well_desc struct that we initialize during compile time. For the rest of the dynamic fields allocate an array of i915_power_well objects in i915 dev_priv, and link to each of these objects their corresponding i915_power_well_desc object. v2: - Fix checkpatch warnings about missing param name in fn declaration and lines over 80 chars. (Paulo) - Move check for unique IDs to __set_power_wells(). Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180806095843.13294-5-imre.deak@intel.com
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