Commit cbe7a9be authored by Kristina Martšenko's avatar Kristina Martšenko

arm64: enable ptrauth earlier

When the kernel is compiled with pointer auth instructions, the boot CPU
needs to start using address auth very early, so change the cpucap to
account for this.

Pointer auth must be enabled before we call C functions, because it is
not possible to enter a function with pointer auth disabled and exit it
with pointer auth enabled. Note, mismatches between architected and
IMPDEF algorithms will still be caught by the cpufeature framework (the
separate *_ARCH and *_IMP_DEF cpucaps).

Note the change in behavior: if the boot CPU has address auth and a late
CPU does not, then we offline the late CPU. Until now we would have just
disabled address auth in this case.

Leave generic authentication as a "system scope" cpucap for now, since
initially the kernel will only use address authentication.
Reviewed-by: default avatarKees Cook <keescook@chromium.org>
Signed-off-by: default avatarKristina Martšenko <kristina.martsenko@arm.com>
parent 66e12279
......@@ -1377,6 +1377,10 @@ config ARM64_PTR_AUTH
be enabled. However, KVM guest also require VHE mode and hence
CONFIG_ARM64_VHE=y option to use this feature.
If the feature is present on the primary CPU but not a secondary CPU,
then the secondary CPU will be offlined. On such a system, this
option should not be selected.
endmenu
config ARM64_SVE
......
......@@ -293,6 +293,15 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
#define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE \
(ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PANIC_ON_CONFLICT)
/*
* CPU feature used early in the boot based on the boot CPU. It is safe for a
* late CPU to have this feature even though the boot CPU hasn't enabled it,
* although the feature will not be used by Linux in this case. If the boot CPU
* has enabled this feature already, then every late CPU must have it.
*/
#define ARM64_CPUCAP_BOOT_CPU_FEATURE \
(ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
struct arm64_cpu_capabilities {
const char *desc;
u16 capability;
......
......@@ -33,6 +33,7 @@
#define CPU_STUCK_REASON_52_BIT_VA (UL(1) << CPU_STUCK_REASON_SHIFT)
#define CPU_STUCK_REASON_NO_GRAN (UL(2) << CPU_STUCK_REASON_SHIFT)
#define CPU_STUCK_REASON_NO_PTRAUTH (UL(4) << CPU_STUCK_REASON_SHIFT)
#ifndef __ASSEMBLY__
......
......@@ -1236,12 +1236,6 @@ static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
#endif /* CONFIG_ARM64_RAS_EXTN */
#ifdef CONFIG_ARM64_PTR_AUTH
static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
{
sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
}
static bool has_address_auth(const struct arm64_cpu_capabilities *entry,
int __unused)
{
......@@ -1518,7 +1512,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
{
.desc = "Address authentication (architected algorithm)",
.capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
.sys_reg = SYS_ID_AA64ISAR1_EL1,
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64ISAR1_APA_SHIFT,
......@@ -1528,7 +1522,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
{
.desc = "Address authentication (IMP DEF algorithm)",
.capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
.sys_reg = SYS_ID_AA64ISAR1_EL1,
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64ISAR1_API_SHIFT,
......@@ -1537,9 +1531,8 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
},
{
.capability = ARM64_HAS_ADDRESS_AUTH,
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
.matches = has_address_auth,
.cpu_enable = cpu_enable_address_auth,
},
{
.desc = "Generic authentication (architected algorithm)",
......
......@@ -24,6 +24,7 @@
#include <linux/init.h>
#include <linux/irqchip/arm-gic-v3.h>
#include <asm/alternative.h>
#include <asm/assembler.h>
#include <asm/boot.h>
#include <asm/ptrace.h>
......@@ -128,6 +129,8 @@ ENTRY(stext)
* the TCR will have been set.
*/
bl __cpu_setup // initialise processor
mov x1, #1
bl __ptrauth_setup
b __primary_switch
ENDPROC(stext)
......@@ -722,6 +725,8 @@ secondary_startup:
*/
bl __cpu_secondary_check52bitva
bl __cpu_setup // initialise processor
mov x1, #0
bl __ptrauth_setup
adrp x1, swapper_pg_dir
bl __enable_mmu
ldr x8, =__secondary_switched
......@@ -829,6 +834,51 @@ __no_granule_support:
b 1b
ENDPROC(__no_granule_support)
/*
* Enable pointer authentication.
* x0 = SCTLR_EL1
* x1 = 1 for primary, 0 for secondary
*/
__ptrauth_setup:
#ifdef CONFIG_ARM64_PTR_AUTH
/* Check if the CPU supports ptrauth */
mrs x2, id_aa64isar1_el1
ubfx x2, x2, #ID_AA64ISAR1_APA_SHIFT, #8
cbz x2, 2f
/* x2 = system_supports_address_auth() */
alternative_if ARM64_HAS_ADDRESS_AUTH
mov x2, 1
alternative_else
mov x2, 0
alternative_endif
orr x2, x2, x1 // primary || system_supports_address_auth()
cbz x2, 3f
/* Enable ptrauth instructions */
ldr x2, =SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | \
SCTLR_ELx_ENDA | SCTLR_ELx_ENDB
orr x0, x0, x2
b 3f
2: /* No ptrauth support */
alternative_if ARM64_HAS_ADDRESS_AUTH
b 4f
alternative_else_nop_endif
3:
#endif
ret
#ifdef CONFIG_ARM64_PTR_AUTH
4: /* Park the secondary CPU */
update_early_cpu_boot_status \
CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_PTRAUTH, x0, x1
5: wfe
wfi
b 5b
#endif
ENDPROC(__ptrauth_setup)
#ifdef CONFIG_RELOCATABLE
__relocate_kernel:
/*
......
......@@ -171,6 +171,8 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
pr_crit("CPU%u: does not support 52-bit VAs\n", cpu);
if (status & CPU_STUCK_REASON_NO_GRAN)
pr_crit("CPU%u: does not support %luK granule \n", cpu, PAGE_SIZE / SZ_1K);
if (status & CPU_STUCK_REASON_NO_PTRAUTH)
pr_crit("CPU%u: does not support pointer authentication\n", cpu);
cpus_stuck_in_kernel++;
break;
case CPU_PANIC_KERNEL:
......
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