Commit a75e551a authored by Akash Bagdia's avatar Akash Bagdia Committed by Chris Emmons

gem5-energy: Update dvfs config and dts files

Modified defconfig and dtses' to sync with latest mobile like gem5 baseline.
Updated gem5 cpufreq drivers to avoid registering when dvfs handler is
disabled in the gem5 hardware.
parent 325b404d
......@@ -44,11 +44,6 @@
core0: core@0 {
reg = <0>;
};
/*
core1: core@1 {
reg = <1>;
};
*/
};
};
};
......@@ -65,15 +60,6 @@
core = <&core0>;
clock-frequency = <1000000000>;
};
/* cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
cluster = <&cluster0>;
core = <&core1>;
reg = <1>;
};
*/
};
memory@80000000 {
......@@ -87,8 +73,9 @@
interrupts = <0 85 4>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
mode = "1024x768-16@60";
// mode = "3840x2160M-16@60m"; // 4K mode string
// mode = "1024x768MR-16@60";
mode = "1920x1080MR-16@60"; // HD mode string
// mode = "3840x2160MR-16@60"; // UHD4K mode string
framebuffer = <0 0x8f000000 0 0x01000000>;
};
/*
......@@ -181,7 +168,7 @@
gem5_energy_ctrl@1c080000 {
compatible = "arm,gem5-energy-ctrl";
reg = <0 0x1c080000 0 0x1C>;
reg = <0 0x1c080000 0 0x1000>;
};
dcc {
......
......@@ -87,8 +87,9 @@
interrupts = <0 85 4>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
mode = "1024x768-16@60";
// mode = "3840x2160M-16@60m"; // 4K mode string
// mode = "1024x768MR-16@60";
mode = "1920x1080MR-16@60"; // HD mode string
// mode = "3840x2160MR-16@60"; // UHD4K mode string
framebuffer = <0 0x8f000000 0 0x01000000>;
};
/*
......@@ -181,7 +182,7 @@
gem5_energy_ctrl@1c080000 {
compatible = "arm,gem5-energy-ctrl";
reg = <0 0x1c080000 0 0x1C>;
reg = <0 0x1c080000 0 0x1000>;
};
dcc {
......
......@@ -111,8 +111,9 @@
interrupts = <0 85 4>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
mode = "1024x768-16@60";
// mode = "3840x2160M-16@60m"; // 4K mode string
// mode = "1024x768MR-16@60";
mode = "1920x1080MR-16@60"; // HD mode string
// mode = "3840x2160MR-16@60"; // UHD4K mode string
framebuffer = <0 0x8f000000 0 0x01000000>;
};
/*
......@@ -205,7 +206,7 @@
gem5_energy_ctrl@1c080000 {
compatible = "arm,gem5-energy-ctrl";
reg = <0 0x1c080000 0 0x1C>;
reg = <0 0x1c080000 0 0x1000>;
};
dcc {
......
......@@ -94,8 +94,9 @@
interrupts = <0 85 4>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
mode = "1024x768-16@60";
// mode = "3840x2160M-16@60m"; // 4K mode string
// mode = "1024x768MR-16@60";
mode = "1920x1080MR-16@60"; // HD mode string
// mode = "3840x2160MR-16@60"; // UHD4K mode string
framebuffer = <0 0x8f000000 0 0x01000000>;
};
/*
......@@ -188,7 +189,7 @@
gem5_energy_ctrl@1c080000 {
compatible = "arm,gem5-energy-ctrl";
reg = <0 0x1c080000 0 0x1C>;
reg = <0 0x1c080000 0 0x1000>;
};
dcc {
......
......@@ -133,8 +133,9 @@
interrupts = <0 85 4>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
mode = "1024x768-16@60";
// mode = "3840x2160M-16@60m"; // 4K mode string
// mode = "1024x768MR-16@60";
mode = "1920x1080MR-16@60"; // HD mode string
// mode = "3840x2160MR-16@60"; // UHD4K mode string
framebuffer = <0 0x8f000000 0 0x01000000>;
};
/*
......@@ -227,7 +228,7 @@
gem5_energy_ctrl@1c080000 {
compatible = "arm,gem5-energy-ctrl";
reg = <0 0x1c080000 0 0x1C>;
reg = <0 0x1c080000 0 0x1000>;
};
dcc {
......
......@@ -30,6 +30,7 @@ CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_VEXPRESS_GEM5=y
# CONFIG_SWP_EMULATE is not set
CONFIG_SMP=y
CONFIG_NR_CPUS=8
CONFIG_SCHED_MC=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_MCPM=y
......@@ -40,6 +41,7 @@ CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_SCHED_HRTICK=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE=""
......@@ -179,7 +181,7 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
......@@ -189,6 +191,9 @@ CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_FTRACE=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_DEBUG_PREEMPT=n
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_BINARY_PRINTF=y
......
......@@ -64,6 +64,12 @@ static bool gem5_energy_ctrl_initialized(void)
return gem5_energy_ctrl_load_result == 0;
}
bool gem5_energy_ctrl_dvfs_enabled(void)
{
return info->dvfs_handler_status;
}
EXPORT_SYMBOL_GPL(gem5_energy_ctrl_dvfs_enabled);
static u32 index_of_domain_id(u32 domain_id)
{
u32 i;
......@@ -157,6 +163,8 @@ int gem5_energy_ctrl_set_performance(u32 domain_id, u32 freq)
int ret, perf;
u32 domain_index;
ret = 0;
if (!gem5_energy_ctrl_initialized() || !info->dvfs_handler_status)
return -EINVAL;
......@@ -246,8 +254,8 @@ int gem5_energy_ctrl_get_opp_table(u32 domain_id, u32 **fptr, u32 **vptr)
{
u32 domain_index;
if (!gem5_energy_ctrl_initialized() ||
WARN_ON_ONCE(!fptr || !info->dvfs_handler_status))
if (!gem5_energy_ctrl_initialized() || !fptr || !vptr || !info ||
!info->dvfs_handler_status)
return -EINVAL;
domain_index = index_of_domain_id(domain_id);
......
......@@ -81,6 +81,14 @@ static int gem5_mc_init(void)
return -ENOENT;
}
if (!gem5_energy_ctrl_dvfs_enabled()) {
pr_info("%s: DVFS handler in energy controller is disabled, \
ARM gem5 multi-cluster cpufreq driver \
will not be registered\n",
__func__);
return -ENOENT;
}
return mc_cpufreq_register(&gem5_mc_ops);
}
module_init(gem5_mc_init);
......
......@@ -19,6 +19,7 @@
/* Energy Controller */
extern bool gem5_energy_ctrl_check_loaded(void);
extern bool gem5_energy_ctrl_dvfs_enabled(void);
extern u32 gem5_energy_ctrl_get_trans_latency(void);
extern int gem5_energy_ctrl_get_opp_table(u32, u32 **, u32 **);
extern int gem5_energy_ctrl_get_performance(u32, u32 *);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment