Commit e588f77a authored by Christopher Daniel Emmons's avatar Christopher Daniel Emmons Committed by Chris Emmons

Baseline retrofit of older pcie and gem5-specific support

Signed-off-by: default avatarChristopher Daniel Emmons <chris.emmons@arm.com>
parent 3f169e18
......@@ -244,8 +244,10 @@ else
MACHINE :=
endif
ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
ifneq ($(CONFIG_ARCH_VEXPRESS_GEM5),y)
MACHINE :=
endif
endif
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
......@@ -258,6 +260,15 @@ KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
endif
endif
ifeq ($(CONFIG_ARCH_VEXPRESS_GEM5),y)
ifeq ($(KBUILD_SRC),)
KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
else
KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
endif
endif
export TEXT_OFFSET GZFLAGS MMUEXT
# Do we have FASTFPE?
......
......@@ -12,8 +12,10 @@
#
ifneq ($(MACHINE),)
ifneq ($(CONFIG_ARCH_VEXPRESS_GEM5),y)
include $(srctree)/$(MACHINE)/Makefile.boot
endif
endif
include $(srctree)/arch/arm/boot/dts/Makefile
# Note: the following conditions must always be true:
......
......@@ -315,6 +315,7 @@ dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
vexpress-v2p-ca9.dtb \
vexpress-v2p-ca15-tc1.dtb \
vexpress-v2p-ca15-tc1-gem5.dtb \
vexpress-v2p-ca15_a7.dtb \
rtsm_ve-cortex_a9x2.dtb \
rtsm_ve-cortex_a9x4.dtb \
......
/*
* ARM Ltd. Versatile Express
*
* Motherboard Express uATX
* V2M-P1
*
* HBI-0190D
*
* RS1 memory map ("ARM Cortex-A Series memory map" in the board's
* Technical Reference Manual)
*
* WARNING! The hardware described in this file is independent from the
* original variant (vexpress-v2m.dtsi), but there is a strong
* correspondence between the two configurations.
*
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
* CHANGES TO vexpress-v2m.dtsi!
*/
motherboard {
model = "V2M-P1";
arm,hbi = <0x190>;
arm,vexpress,site = <0>;
arm,v2m-memory-map = "rs1";
compatible = "arm,vexpress,v2m-p1", "simple-bus";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
#interrupt-cells = <1>;
ranges;
/*
* Note: The pcie is probably not perfect.
* It was created to support IDE for gem5.
*/
pci: gem5_pcie@0x30000000 {
compatible = "arm,gem5_pcie","pci";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0x30000000 0x1000000>; /* Configuration Space */
virtual-reg = <0xf0000000>; /* Virtual address - cfg space*/
bus-range = <0 0>;
/* currently only 3 ranges accepted: MEM, MEMP & IO */
ranges = <0x42000000 0 0x41000000 0 0x41000000 0 0x01000000
/* ^- Prefetchable-Memory Space */
0x02000000 0 0x40000000 0 0x40000000 0 0x01000000
/* ^-Non-Prefetchable Mem Space */
0x01000000 0 0x2f000000 0 0x2f000000 0 0x00010000>;
/* ^-IO Space */
interrupt-parent = <&gic>;
interrupts = <17>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &gic 0 49 4
0000 0 0 2 &gic 0 50 4
0000 0 0 3 &gic 0 51 4
0000 0 0 4 &gic 0 52 4
>;
};
flash@0,00000000 {
compatible = "arm,vexpress-flash", "cfi-flash";
reg = <0 0x00000000 0x04000000>,
<4 0x00000000 0x04000000>;
bank-width = <4>;
};
psram@1,00000000 {
compatible = "arm,vexpress-psram", "mtd-ram";
reg = <1 0x00000000 0x02000000>;
bank-width = <4>;
};
vram@2,00000000 {
compatible = "arm,vexpress-vram";
reg = <2 0x00000000 0x00800000>;
};
ethernet@2,02000000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <2 0x02000000 0x10000>;
interrupts = <15>;
phy-mode = "mii";
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
vdd33a-supply = <&v2m_fixed_3v3>;
vddvario-supply = <&v2m_fixed_3v3>;
};
usb@2,03000000 {
compatible = "nxp,usb-isp1761";
reg = <2 0x03000000 0x20000>;
interrupts = <16>;
port1-otg;
};
iofpga@3,00000000 {
compatible = "arm,amba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysreg: sysreg@010000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};
v2m_sysctl: sysctl@020000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
};
/* PCI-E I2C bus */
v2m_i2c_pcie: i2c@030000 {
compatible = "arm,versatile-i2c";
reg = <0x030000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
pcie-switch@60 {
compatible = "idt,89hpes32h8";
reg = <0x60>;
};
};
aaci@040000 {
compatible = "arm,pl041", "arm,primecell";
reg = <0x040000 0x1000>;
interrupts = <11>;
clocks = <&smbclk>;
clock-names = "apb_pclk";
};
mmci@050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
interrupts = <9 10>;
cd-gpios = <&v2m_sysreg 0 0>;
wp-gpios = <&v2m_sysreg 1 0>;
max-frequency = <12000000>;
vmmc-supply = <&v2m_fixed_3v3>;
clocks = <&v2m_clk24mhz>, <&smbclk>;
clock-names = "mclk", "apb_pclk";
};
kmi@060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x060000 0x1000>;
interrupts = <12>;
clocks = <&v2m_clk24mhz>, <&smbclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x070000 0x1000>;
interrupts = <13>;
clocks = <&v2m_clk24mhz>, <&smbclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
v2m_serial0: uart@090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial1: uart@0a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial2: uart@0b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial3: uart@0c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
clocks = <&v2m_oscclk2>, <&smbclk>;
clock-names = "uartclk", "apb_pclk";
};
wdt@0f0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0f0000 0x1000>;
interrupts = <0>;
clocks = <&v2m_refclk32khz>, <&smbclk>;
clock-names = "wdogclk", "apb_pclk";
};
v2m_timer01: timer@110000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x110000 0x1000>;
interrupts = <2>;
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
v2m_timer23: timer@120000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x120000 0x1000>;
interrupts = <3>;
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
/* DVI I2C bus */
v2m_i2c_dvi: i2c@160000 {
compatible = "arm,versatile-i2c";
reg = <0x160000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
dvi-transmitter@39 {
compatible = "sil,sii9022-tpi", "sil,sii9022";
reg = <0x39>;
};
dvi-transmitter@60 {
compatible = "sil,sii9022-cpi", "sil,sii9022";
reg = <0x60>;
};
};
rtc@170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x170000 0x1000>;
interrupts = <4>;
clocks = <&smbclk>;
clock-names = "apb_pclk";
};
compact-flash@1a0000 {
compatible = "arm,vexpress-cf", "ata-generic";
reg = <0x1a0000 0x100
0x1a0100 0xf00>;
reg-shift = <2>;
};
clcd@1f0000 {
status = "disabled";
compatible = "arm,pl111", "arm,primecell";
reg = <0x1f0000 0x1000>;
interrupts = <14>;
clocks = <&v2m_oscclk1>, <&smbclk>;
clock-names = "clcdclk", "apb_pclk";
};
};
v2m_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
osc@0 {
/* MCC static memory clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
freq-range = <25000000 60000000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk0";
};
v2m_oscclk1: osc@1 {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
freq-range = <23750000 63500000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk1";
};
v2m_oscclk2: osc@2 {
/* IO FPGA peripheral clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
freq-range = <24000000 24000000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk2";
};
volt@0 {
/* Logic level voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
regulator-name = "VIO";
regulator-always-on;
label = "VIO";
};
temp@0 {
/* MCC internal operating temperature */
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "MCC";
};
reset@0 {
compatible = "arm,vexpress-reset";
arm,vexpress-sysreg,func = <5 0>;
};
muxfpga@0 {
compatible = "arm,vexpress-muxfpga";
arm,vexpress-sysreg,func = <7 0>;
};
shutdown@0 {
compatible = "arm,vexpress-shutdown";
arm,vexpress-sysreg,func = <8 0>;
};
reboot@0 {
compatible = "arm,vexpress-reboot";
arm,vexpress-sysreg,func = <9 0>;
};
dvimode@0 {
compatible = "arm,vexpress-dvimode";
arm,vexpress-sysreg,func = <11 0>;
};
};
};
/*
* ARM Ltd. Versatile Express
*
* CoreTile Express A15x2 (version with Test Chip 1)
* Cortex-A15 MPCore (V2P-CA15)
*
* HBI-0237A
*/
/dts-v1/;
/memreserve/ 0xbf000000 0x01000000;
/ {
model = "V2P-CA15";
arm,hbi = <0x0>;
arm,vexpress,site = <0xf>;
compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
i2c0 = &v2m_i2c_dvi;
i2c1 = &v2m_i2c_pcie;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
clock-frequency = <1000000000>;
};
/* cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
*/
};
memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0 0x2b000000 0 0x1000>;
interrupts = <0 85 4>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
mode = "1024x768-16@60";
framebuffer = <0 0xbf000000 0 0x01000000>;
};
/*
memory-controller@2b0a0000 {
compatible = "arm,pl341", "arm,primecell";
reg = <0 0x2b0a0000 0 0x1000>;
clocks = <&oscclk7>;
clock-names = "apb_pclk";
};
*/
/*
wdt@2b060000 {
compatible = "arm,sp805", "arm,primecell";
status = "disabled";
reg = <0 0x2b060000 0 0x1000>;
interrupts = <0 98 4>;
clocks = <&oscclk7>;
clock-names = "apb_pclk";
};
*/
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x2c001000 0 0x1000>,
<0 0x2c002000 0 0x1000>,
<0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
/*
memory-controller@7ffd0000 {
compatible = "arm,pl354", "arm,primecell";
reg = <0 0x7ffd0000 0 0x1000>;
interrupts = <0 86 4>,
<0 87 4>;
clocks = <&oscclk7>;
clock-names = "apb_pclk";
};
*/
/*
dma@7ffb0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0 0x7ffb0000 0 0x1000>;
interrupts = <0 92 4>,
<0 88 4>,
<0 89 4>,
<0 90 4>,
<0 91 4>;
clocks = <&oscclk7>;
clock-names = "apb_pclk";
};
*/
/*
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
*/
/** HACK : cortex-a9-twd-timer hack -- temporary fix */
timer@2c080000 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0 0x2c080000 0 0x20>;
interrupts = <1 13 0xf04>;
clocks = <&oscclk7>;
clock-names = "apb_pclk";
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <0 68 4>,
<0 69 4>;
};
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
osc@0 {
/* CPU PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
freq-range = <50000000 60000000>;
#clock-cells = <0>;
clock-output-names = "oscclk0";
};
osc@4 {
/* Multiplexed AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
freq-range = <20000000 40000000>;
#clock-cells = <0>;
clock-output-names = "oscclk4";
};
oscclk5: osc@5 {
/* HDLCD PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
freq-range = <23750000 165000000>;
#clock-cells = <0>;
clock-output-names = "oscclk5";
};
smbclk: osc@6 {
/* SMB clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 6>;
freq-range = <20000000 50000000>;
#clock-cells = <0>;
clock-output-names = "oscclk6";
};
oscclk7: osc@7 {
/* SYS PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 7>;
freq-range = <20000000 60000000>;
#clock-cells = <0>;
clock-output-names = "oscclk7";
};
osc@8 {
/* DDR2 PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 8>;
freq-range = <40000000 40000000>;
#clock-cells = <0>;
clock-output-names = "oscclk8";
};
volt@0 {
/* CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
regulator-name = "Cores";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
label = "Cores";
};
amp@0 {
/* Total current for the two cores */
compatible = "arm,vexpress-amp";
arm,vexpress-sysreg,func = <3 0>;
label = "Cores";
};
temp@0 {
/* DCC internal temperature */
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "DCC";
};
power@0 {
/* Total power */
compatible = "arm,vexpress-power";
arm,vexpress-sysreg,func = <12 0>;
label = "Cores";
};
energy@0 {
/* Total energy */
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 0>;
label = "Cores";
};
};
smb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,