Kconfig 64.7 KB
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# SPDX-License-Identifier: GPL-2.0
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config ARM
	bool
	default y
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	select ARCH_32BIT_OFF_T
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	select ARCH_CLOCKSOURCE_DATA
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	select ARCH_HAS_BINFMT_FLAT
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	select ARCH_HAS_DEBUG_VIRTUAL if MMU
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	select ARCH_HAS_DEVMEM_IS_ALLOWED
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	select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
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	select ARCH_HAS_ELF_RANDOMIZE
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	select ARCH_HAS_FORTIFY_SOURCE
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	select ARCH_HAS_KEEPINITRD
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	select ARCH_HAS_KCOV
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	select ARCH_HAS_MEMBARRIER_SYNC_CORE
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	select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
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	select ARCH_HAS_PHYS_TO_DMA
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	select ARCH_HAS_SETUP_DMA_OPS
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	select ARCH_HAS_SET_MEMORY
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	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
	select ARCH_HAS_STRICT_MODULE_RWX if MMU
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	select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
	select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
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	select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
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	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
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	select ARCH_HAVE_CUSTOM_GPIO_H
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	select ARCH_HAS_GCOV_PROFILE_ALL
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	select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC
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	select ARCH_MIGHT_HAVE_PC_PARPORT
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	select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
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	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
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	select ARCH_SUPPORTS_ATOMIC_RMW
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	select ARCH_USE_BUILTIN_BSWAP
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	select ARCH_USE_CMPXCHG_LOCKREF
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	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
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	select ARCH_WANT_IPC_PARSE_VERSION
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	select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
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	select BUILDTIME_EXTABLE_SORT if MMU
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	select CLONE_BACKWARDS
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	select CPU_PM if SUSPEND || CPU_IDLE
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	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
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	select DMA_DECLARE_COHERENT
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	select DMA_REMAP if MMU
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	select EDAC_SUPPORT
	select EDAC_ATOMIC_SCRUB
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	select GENERIC_ALLOCATOR
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	select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
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	select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
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	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
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	select GENERIC_CPU_AUTOPROBE
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	select GENERIC_EARLY_IOREMAP
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	select GENERIC_IDLE_POLL_SETUP
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	select GENERIC_IRQ_PROBE
	select GENERIC_IRQ_SHOW
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	select GENERIC_IRQ_SHOW_LEVEL
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	select GENERIC_PCI_IOMAP
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	select GENERIC_SCHED_CLOCK
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	select GENERIC_SMP_IDLE_THREAD
	select GENERIC_STRNCPY_FROM_USER
	select GENERIC_STRNLEN_USER
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	select HANDLE_DOMAIN_IRQ
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	select HARDIRQS_SW_RESEND
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	select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
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	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
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	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
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	select HAVE_ARCH_MMAP_RND_BITS if MMU
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	select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
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	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
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	select HAVE_ARCH_TRACEHOOK
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	select HAVE_ARM_SMCCC if CPU_V7
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	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
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	select HAVE_CONTEXT_TRACKING
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	select HAVE_COPY_THREAD_TLS
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	select HAVE_C_RECORDMCOUNT
	select HAVE_DEBUG_KMEMLEAK
	select HAVE_DMA_CONTIGUOUS if MMU
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	select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
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	select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
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	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
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	select HAVE_EXIT_THREAD
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	select HAVE_FAST_GUP if ARM_LPAE
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	select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
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	select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
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	select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000)
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	select HAVE_GCC_PLUGINS
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	select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
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	select HAVE_IDE if PCI || ISA || PCMCIA
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	select HAVE_IRQ_TIME_ACCOUNTING
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	select HAVE_KERNEL_GZIP
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	select HAVE_KERNEL_LZ4
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	select HAVE_KERNEL_LZMA
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	select HAVE_KERNEL_LZO
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	select HAVE_KERNEL_XZ
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	select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
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	select HAVE_KRETPROBES if HAVE_KPROBES
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	select HAVE_MOD_ARCH_SPECIFIC
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	select HAVE_NMI
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	select HAVE_OPROFILE if HAVE_PERF_EVENTS
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	select HAVE_OPTPROBES if !THUMB2_KERNEL
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	select HAVE_PERF_EVENTS
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	select HAVE_PERF_REGS
	select HAVE_PERF_USER_STACK_DUMP
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	select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
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	select HAVE_REGS_AND_STACK_ACCESS_API
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	select HAVE_RSEQ
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	select HAVE_STACKPROTECTOR
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	select HAVE_SYSCALL_TRACEPOINTS
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	select HAVE_UID16
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	select HAVE_VIRT_CPU_ACCOUNTING_GEN
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	select IRQ_FORCED_THREADING
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	select MODULES_USE_ELF_REL
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	select NEED_DMA_MAP_STATE
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	select OF_EARLY_FLATTREE if OF
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	select OLD_SIGACTION
	select OLD_SIGSUSPEND3
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	select PCI_SYSCALL if PCI
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	select PERF_USE_VMALLOC
	select RTC_LIB
	select SYS_SUPPORTS_APM_EMULATION
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	# Above selects are sorted alphabetically; please add new ones
	# according to that.  Thanks.
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	help
	  The ARM series is a line of low-power-consumption RISC chip designs
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	  licensed by ARM Ltd and targeted at embedded applications and
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	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
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	  manufactured, but legacy ARM-based PC hardware remains popular in
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	  Europe.  There is an ARM Linux project with a web page at
	  <http://www.arm.linux.org.uk/>.

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config ARM_HAS_SG_CHAIN
	bool

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config ARM_DMA_USE_IOMMU
	bool
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	select ARM_HAS_SG_CHAIN
	select NEED_SG_DMA_LENGTH
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if ARM_DMA_USE_IOMMU

config ARM_DMA_IOMMU_ALIGNMENT
	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
	range 4 9
	default 8
	help
	  DMA mapping framework by default aligns all buffers to the smallest
	  PAGE_SIZE order which is greater than or equal to the requested buffer
	  size. This works well for buffers up to a few hundreds kilobytes, but
	  for larger buffers it just a waste of address space. Drivers which has
	  relatively small addressing window (like 64Mib) might run out of
	  virtual space with just a few allocations.

	  With this parameter you can specify the maximum PAGE_SIZE order for
	  DMA IOMMU buffers. Larger buffers will be aligned only to this
	  specified order. The order is expressed as a power of two multiplied
	  by the PAGE_SIZE.

endif

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config SYS_SUPPORTS_APM_EMULATION
	bool

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config HAVE_TCM
	bool
	select GENERIC_ALLOCATOR

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config HAVE_PROC_CPU
	bool

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config NO_IOPORT_MAP
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	bool

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config SBUS
	bool

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config STACKTRACE_SUPPORT
	bool
	default y

config LOCKDEP_SUPPORT
	bool
	default y

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config TRACE_IRQFLAGS_SUPPORT
	bool
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	default !CPU_V7M
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config ARCH_HAS_ILOG2_U32
	bool

config ARCH_HAS_ILOG2_U64
	bool

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config ARCH_HAS_BANDGAP
	bool

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config FIX_EARLYCON_MEM
	def_bool y if MMU

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config GENERIC_HWEIGHT
	bool
	default y

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config GENERIC_CALIBRATE_DELAY
	bool
	default y

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config ARCH_MAY_HAVE_PC_FDC
	bool

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config ZONE_DMA
	bool

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config ARCH_SUPPORTS_UPROBES
	def_bool y

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config ARCH_HAS_DMA_SET_COHERENT_MASK
	bool

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config GENERIC_ISA_DMA
	bool

config FIQ
	bool

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config NEED_RET_TO_USER
	bool

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config ARCH_MTD_XIP
	bool

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config ARM_PATCH_PHYS_VIRT
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	bool "Patch physical to virtual translations at runtime" if EMBEDDED
	default y
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	depends on !XIP_KERNEL && MMU
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	help
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	  Patch phys-to-virt and virt-to-phys translation functions at
	  boot and module load time according to the position of the
	  kernel in system memory.
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	  This can only be used with non-XIP MMU kernels where the base
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	  of physical memory is at a 16MB boundary.
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	  Only disable this option if you know that you do not require
	  this feature (eg, building a kernel for a single machine) and
	  you need to shrink the kernel to the minimal size.
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config NEED_MACH_IO_H
	bool
	help
	  Select this when mach/io.h is required to provide special
	  definitions for this platform.  The need for mach/io.h should
	  be avoided when possible.

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config NEED_MACH_MEMORY_H
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	bool
	help
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	  Select this when mach/memory.h is required to provide special
	  definitions for this platform.  The need for mach/memory.h should
	  be avoided when possible.
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config PHYS_OFFSET
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	hex "Physical address of main memory" if MMU
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	depends on !ARM_PATCH_PHYS_VIRT
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	default DRAM_BASE if !MMU
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	default 0x00000000 if ARCH_EBSA110 || \
			ARCH_FOOTBRIDGE || \
			ARCH_INTEGRATOR || \
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			ARCH_REALVIEW
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	default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
	default 0x20000000 if ARCH_S5PV210
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	default 0xc0000000 if ARCH_SA1100
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	help
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	  Please provide the physical address corresponding to the
	  location of main memory in your system.
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config GENERIC_BUG
	def_bool y
	depends on BUG

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config PGTABLE_LEVELS
	int
	default 3 if ARM_LPAE
	default 2

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menu "System Type"

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config MMU
	bool "MMU-based Paged Memory Management Support"
	default y
	help
	  Select if you want MMU-based virtualised addressing space
	  support by paged memory management. If unsure, say 'Y'.

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config ARCH_MMAP_RND_BITS_MIN
	default 8

config ARCH_MMAP_RND_BITS_MAX
	default 14 if PAGE_OFFSET=0x40000000
	default 15 if PAGE_OFFSET=0x80000000
	default 16

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#
# The "ARM system type" choice list is ordered alphabetically by option
# text.  Please add new entries in the option alphabetic order.
#
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choice
	prompt "ARM system type"
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	default ARM_SINGLE_ARMV7M if !MMU
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	default ARCH_MULTIPLATFORM if MMU
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config ARCH_MULTIPLATFORM
	bool "Allow multiple platforms to be selected"
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	depends on MMU
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	select ARM_HAS_SG_CHAIN
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	select ARM_PATCH_PHYS_VIRT
	select AUTO_ZRELADDR
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	select TIMER_OF
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	select COMMON_CLK
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	select GENERIC_CLOCKEVENTS
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	select GENERIC_IRQ_MULTI_HANDLER
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	select HAVE_PCI
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	select PCI_DOMAINS_GENERIC if PCI
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	select SPARSE_IRQ
	select USE_OF

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config ARM_SINGLE_ARMV7M
	bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
	depends on !MMU
	select ARM_NVIC
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	select AUTO_ZRELADDR
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	select TIMER_OF
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	select COMMON_CLK
	select CPU_V7M
	select GENERIC_CLOCKEVENTS
	select NO_IOPORT_MAP
	select SPARSE_IRQ
	select USE_OF

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config ARCH_EBSA110
	bool "EBSA-110"
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	select ARCH_USES_GETTIMEOFFSET
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	select CPU_SA110
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	select ISA
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	select NEED_MACH_IO_H
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	select NEED_MACH_MEMORY_H
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	select NO_IOPORT_MAP
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	help
	  This is an evaluation board for the StrongARM processor available
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	  from Digital. It has limited hardware on-board, including an
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	  Ethernet interface, two PCMCIA sockets, two serial ports and a
	  parallel port.

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config ARCH_EP93XX
	bool "EP93xx-based"
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	select ARCH_SPARSEMEM_ENABLE
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	select ARM_AMBA
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	imply ARM_PATCH_PHYS_VIRT
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	select ARM_VIC
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	select AUTO_ZRELADDR
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	select CLKDEV_LOOKUP
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	select CLKSRC_MMIO
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	select CPU_ARM920T
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	select GENERIC_CLOCKEVENTS
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	select GPIOLIB
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	help
	  This enables support for the Cirrus EP93xx series of CPUs.

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config ARCH_FOOTBRIDGE
	bool "FootBridge"
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	select CPU_SA110
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	select FOOTBRIDGE
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	select GENERIC_CLOCKEVENTS
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	select HAVE_IDE
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	select NEED_MACH_IO_H if !MMU
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	select NEED_MACH_MEMORY_H
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	help
	  Support for systems based on the DC21285 companion chip
	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
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config ARCH_IOP32X
	bool "IOP32x-based"
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	depends on MMU
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	select CPU_XSCALE
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	select GPIO_IOP
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	select GPIOLIB
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	select NEED_RET_TO_USER
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	select FORCE_PCI
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	select PLAT_IOP
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	help
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	  Support for Intel's 80219 and IOP32X (XScale) family of
	  processors.

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config ARCH_IXP4XX
	bool "IXP4xx-based"
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	depends on MMU
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	select ARCH_HAS_DMA_SET_COHERENT_MASK
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	select ARCH_SUPPORTS_BIG_ENDIAN
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	select CPU_XSCALE
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	select DMABOUNCE if PCI
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	select GENERIC_CLOCKEVENTS
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	select GENERIC_IRQ_MULTI_HANDLER
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	select GPIO_IXP4XX
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	select GPIOLIB
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	select HAVE_PCI
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	select IXP4XX_IRQ
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	select IXP4XX_TIMER
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	select NEED_MACH_IO_H
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	select USB_EHCI_BIG_ENDIAN_DESC
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	select USB_EHCI_BIG_ENDIAN_MMIO
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	help
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	  Support for Intel's IXP4XX (XScale) family of processors.
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config ARCH_DOVE
	bool "Marvell Dove"
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	select CPU_PJ4
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	select GENERIC_CLOCKEVENTS
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	select GENERIC_IRQ_MULTI_HANDLER
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	select GPIOLIB
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	select HAVE_PCI
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	select MVEBU_MBUS
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	select PINCTRL
	select PINCTRL_DOVE
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	select PLAT_ORION_LEGACY
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	select SPARSE_IRQ
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	select PM_GENERIC_DOMAINS if PM
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	help
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	  Support for the Marvell Dove SoC 88AP510
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config ARCH_PXA
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	bool "PXA2xx/PXA3xx-based"
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	depends on MMU
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	select ARCH_MTD_XIP
	select ARM_CPU_SUSPEND if PM
	select AUTO_ZRELADDR
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	select COMMON_CLK
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	select CLKDEV_LOOKUP
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	select CLKSRC_PXA
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	select CLKSRC_MMIO
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	select TIMER_OF
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	select CPU_XSCALE if !CPU_XSC3
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	select GENERIC_CLOCKEVENTS
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	select GENERIC_IRQ_MULTI_HANDLER
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	select GPIO_PXA
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	select GPIOLIB
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	select HAVE_IDE
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	select IRQ_DOMAIN
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	select PLAT_PXA
	select SPARSE_IRQ
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	help
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	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
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config ARCH_RPC
	bool "RiscPC"
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	depends on MMU
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	select ARCH_ACORN
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	select ARCH_MAY_HAVE_PC_FDC
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	select ARCH_SPARSEMEM_ENABLE
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	select ARM_HAS_SG_CHAIN
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	select CPU_SA110
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	select FIQ
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	select HAVE_IDE
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	select HAVE_PATA_PLATFORM
	select ISA_DMA_API
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	select NEED_MACH_IO_H
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	select NEED_MACH_MEMORY_H
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	select NO_IOPORT_MAP
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	help
	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
	  CD-ROM interface, serial and parallel port, and the floppy drive.

config ARCH_SA1100
	bool "SA1100-based"
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	select ARCH_MTD_XIP
	select ARCH_SPARSEMEM_ENABLE
	select CLKDEV_LOOKUP
	select CLKSRC_MMIO
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	select CLKSRC_PXA
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	select TIMER_OF if OF
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	select COMMON_CLK
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	select CPU_FREQ
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	select CPU_SA1100
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	select GENERIC_CLOCKEVENTS
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	select GENERIC_IRQ_MULTI_HANDLER
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	select GPIOLIB
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	select HAVE_IDE
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	select IRQ_DOMAIN
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	select ISA
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	select NEED_MACH_MEMORY_H
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	select SPARSE_IRQ
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	help
	  Support for StrongARM 11x0 based boards.
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config ARCH_S3C24XX
	bool "Samsung S3C24XX SoCs"
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	select ATAGS
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	select CLKDEV_LOOKUP
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	select CLKSRC_SAMSUNG_PWM
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	select GENERIC_CLOCKEVENTS
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	select GPIO_SAMSUNG
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	select GPIOLIB
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	select GENERIC_IRQ_MULTI_HANDLER
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	select HAVE_S3C2410_I2C if I2C
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	select HAVE_S3C2410_WATCHDOG if WATCHDOG
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	select HAVE_S3C_RTC if RTC_CLASS
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	select NEED_MACH_IO_H
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	select SAMSUNG_ATAGS
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	select USE_OF
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	help
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	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
	  Samsung SMDK2410 development board (and derivatives).
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config ARCH_OMAP1
	bool "TI OMAP1"
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	depends on MMU
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	select ARCH_HAS_HOLES_MEMORYMODEL
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	select ARCH_OMAP
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	select CLKDEV_LOOKUP
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	select CLKSRC_MMIO
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	select GENERIC_CLOCKEVENTS
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	select GENERIC_IRQ_CHIP
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	select GENERIC_IRQ_MULTI_HANDLER
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	select GPIOLIB
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	select HAVE_IDE
	select IRQ_DOMAIN
	select NEED_MACH_IO_H if PCCARD
	select NEED_MACH_MEMORY_H
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	select SPARSE_IRQ
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	help
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	  Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
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endchoice

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menu "Multiple platform selection"
	depends on ARCH_MULTIPLATFORM

comment "CPU Core family selection"

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config ARCH_MULTI_V4
	bool "ARMv4 based platforms (FA526)"
	depends on !ARCH_MULTI_V6_V7
	select ARCH_MULTI_V4_V5
	select CPU_FA526

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config ARCH_MULTI_V4T
	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
	depends on !ARCH_MULTI_V6_V7
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	select ARCH_MULTI_V4_V5
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	select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
		CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
		CPU_ARM925T || CPU_ARM940T)
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config ARCH_MULTI_V5
	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
	depends on !ARCH_MULTI_V6_V7
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	select ARCH_MULTI_V4_V5
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	select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
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		CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
		CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
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config ARCH_MULTI_V4_V5
	bool

config ARCH_MULTI_V6
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	bool "ARMv6 based platforms (ARM11)"
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	select ARCH_MULTI_V6_V7
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	select CPU_V6K
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config ARCH_MULTI_V7
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	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
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	default y
	select ARCH_MULTI_V6_V7
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	select CPU_V7
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	select HAVE_SMP
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config ARCH_MULTI_V6_V7
	bool
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	select MIGHT_HAVE_CACHE_L2X0
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config ARCH_MULTI_CPU_AUTO
	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
	select ARCH_MULTI_V5

endmenu

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config ARCH_VIRT
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	bool "Dummy Virtual Machine"
	depends on ARCH_MULTI_V7
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	select ARM_AMBA
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	select ARM_GIC
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	select ARM_GIC_V2M if PCI
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	select ARM_GIC_V3
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	select ARM_GIC_V3_ITS if PCI
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	select ARM_PSCI
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	select HAVE_ARM_ARCH_TIMER
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	select ARCH_SUPPORTS_BIG_ENDIAN
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#
# This is sorted alphabetically by mach-* pathname.  However, plat-*
# Kconfigs may be included either alphabetically (according to the
# plat- suffix) or along side the corresponding mach-* source.
#
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source "arch/arm/mach-actions/Kconfig"

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source "arch/arm/mach-alpine/Kconfig"

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source "arch/arm/mach-artpec/Kconfig"

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source "arch/arm/mach-asm9260/Kconfig"

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source "arch/arm/mach-aspeed/Kconfig"

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source "arch/arm/mach-at91/Kconfig"

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source "arch/arm/mach-axxia/Kconfig"

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source "arch/arm/mach-bcm/Kconfig"

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source "arch/arm/mach-berlin/Kconfig"

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source "arch/arm/mach-clps711x/Kconfig"

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source "arch/arm/mach-cns3xxx/Kconfig"

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source "arch/arm/mach-davinci/Kconfig"

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source "arch/arm/mach-digicolor/Kconfig"

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source "arch/arm/mach-dove/Kconfig"

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source "arch/arm/mach-ep93xx/Kconfig"

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source "arch/arm/mach-exynos/Kconfig"
source "arch/arm/plat-samsung/Kconfig"

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source "arch/arm/mach-footbridge/Kconfig"

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source "arch/arm/mach-gemini/Kconfig"

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source "arch/arm/mach-highbank/Kconfig"

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source "arch/arm/mach-hisi/Kconfig"

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source "arch/arm/mach-imx/Kconfig"

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source "arch/arm/mach-integrator/Kconfig"

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source "arch/arm/mach-iop32x/Kconfig"

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source "arch/arm/mach-ixp4xx/Kconfig"

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source "arch/arm/mach-keystone/Kconfig"

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source "arch/arm/mach-lpc32xx/Kconfig"
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source "arch/arm/mach-mediatek/Kconfig"

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source "arch/arm/mach-meson/Kconfig"

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source "arch/arm/mach-milbeaut/Kconfig"

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source "arch/arm/mach-mmp/Kconfig"
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source "arch/arm/mach-moxart/Kconfig"
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source "arch/arm/mach-mv78xx0/Kconfig"

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source "arch/arm/mach-mvebu/Kconfig"
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source "arch/arm/mach-mxs/Kconfig"

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source "arch/arm/mach-nomadik/Kconfig"

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source "arch/arm/mach-npcm/Kconfig"

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source "arch/arm/mach-nspire/Kconfig"

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source "arch/arm/plat-omap/Kconfig"

source "arch/arm/mach-omap1/Kconfig"
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source "arch/arm/mach-omap2/Kconfig"

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source "arch/arm/mach-orion5x/Kconfig"
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source "arch/arm/mach-oxnas/Kconfig"

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source "arch/arm/mach-picoxcell/Kconfig"

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source "arch/arm/mach-prima2/Kconfig"

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source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"
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source "arch/arm/mach-qcom/Kconfig"

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source "arch/arm/mach-rda/Kconfig"

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source "arch/arm/mach-realview/Kconfig"

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source "arch/arm/mach-rockchip/Kconfig"

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source "arch/arm/mach-s3c24xx/Kconfig"

source "arch/arm/mach-s3c64xx/Kconfig"

source "arch/arm/mach-s5pv210/Kconfig"

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source "arch/arm/mach-sa1100/Kconfig"
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source "arch/arm/mach-shmobile/Kconfig"

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source "arch/arm/mach-socfpga/Kconfig"

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source "arch/arm/mach-spear/Kconfig"
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source "arch/arm/mach-sti/Kconfig"

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source "arch/arm/mach-stm32/Kconfig"

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source "arch/arm/mach-sunxi/Kconfig"

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source "arch/arm/mach-tango/Kconfig"

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source "arch/arm/mach-tegra/Kconfig"

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source "arch/arm/mach-u300/Kconfig"
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source "arch/arm/mach-uniphier/Kconfig"

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source "arch/arm/mach-ux500/Kconfig"
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source "arch/arm/mach-versatile/Kconfig"

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source "arch/arm/mach-vexpress/Kconfig"
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source "arch/arm/plat-versatile/Kconfig"
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source "arch/arm/mach-vt8500/Kconfig"

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source "arch/arm/mach-zx/Kconfig"

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source "arch/arm/mach-zynq/Kconfig"

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# ARMv7-M architecture
config ARCH_EFM32
	bool "Energy Micro efm32"
	depends on ARM_SINGLE_ARMV7M
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	select GPIOLIB
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	help
	  Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
	  processors.

config ARCH_LPC18XX
	bool "NXP LPC18xx/LPC43xx"
	depends on ARM_SINGLE_ARMV7M
	select ARCH_HAS_RESET_CONTROLLER
	select ARM_AMBA
	select CLKSRC_LPC32XX
	select PINCTRL
	help
	  Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
	  high performance microcontrollers.

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config ARCH_MPS2
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	bool "ARM MPS2 platform"
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	depends on ARM_SINGLE_ARMV7M
	select ARM_AMBA
	select CLKSRC_MPS2
	help
	  Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
	  with a range of available cores like Cortex-M3/M4/M7.

	  Please, note that depends which Application Note is used memory map
	  for the platform may vary, so adjustment of RAM base might be needed.

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# Definitions to make life easier
config ARCH_ACORN
	bool

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config PLAT_IOP
	bool
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	select GENERIC_CLOCKEVENTS
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config PLAT_ORION
	bool
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	select CLKSRC_MMIO
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	select COMMON_CLK
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	select GENERIC_IRQ_CHIP
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	select IRQ_DOMAIN
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config PLAT_ORION_LEGACY
	bool
	select PLAT_ORION

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config PLAT_PXA
	bool

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config PLAT_VERSATILE
	bool

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source "arch/arm/mm/Kconfig"
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config IWMMXT
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	bool "Enable iWMMXt support"
	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
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	help
	  Enable support for iWMMXt context switching at run time if
	  running on a CPU that supports it.

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if !MMU
source "arch/arm/Kconfig-nommu"
endif

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config PJ4B_ERRATA_4742
	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
	depends on CPU_PJ4B && MACH_ARMADA_370
	default y
	help
	  When coming out of either a Wait for Interrupt (WFI) or a Wait for
	  Event (WFE) IDLE states, a specific timing sensitivity exists between
	  the retiring WFI/WFE instructions and the newly issued subsequent
	  instructions.  This sensitivity can result in a CPU hang scenario.
	  Workaround:
	  The software must insert either a Data Synchronization Barrier (DSB)
	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE
	  instruction

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config ARM_ERRATA_326103
	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
	depends on CPU_V6
	help
	  Executing a SWP instruction to read-only memory does not set bit 11
	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
	  treat the access as a read, preventing a COW from occurring and
	  causing the faulting task to livelock.

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config ARM_ERRATA_411920
	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
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	depends on CPU_V6 || CPU_V6K
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	help
	  Invalidation of the Instruction Cache operation can
	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
	  It does not affect the MPCore. This option enables the ARM Ltd.
	  recommended workaround.

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config ARM_ERRATA_430973
	bool "ARM errata: Stale prediction on replaced interworking branch"
	depends on CPU_V7
	help
	  This option enables the workaround for the 430973 Cortex-A8
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	  r1p* erratum. If a code sequence containing an ARM/Thumb
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	  interworking branch is replaced with another code sequence at the
	  same virtual address, whether due to self-modifying code or virtual
	  to physical address re-mapping, Cortex-A8 does not recover from the
	  stale interworking branch prediction. This results in Cortex-A8
	  executing the new code sequence in the incorrect ARM or Thumb state.
	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
	  and also flushes the branch target cache at every context switch.
	  Note that setting specific bits in the ACTLR register may not be
	  available in non-secure mode.

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config ARM_ERRATA_458693
	bool "ARM errata: Processor deadlock when a false hazard is created"
	depends on CPU_V7
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	depends on !ARCH_MULTIPLATFORM
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	help
	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
	  erratum. For very specific sequences of memory operations, it is
	  possible for a hazard condition intended for a cache line to instead
	  be incorrectly associated with a different cache line. This false
	  hazard might then cause a processor deadlock. The workaround enables
	  the L1 caching of the NEON accesses and disables the PLD instruction
	  in the ACTLR register. Note that setting specific bits in the ACTLR
	  register may not be available in non-secure mode.

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config ARM_ERRATA_460075
	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
	depends on CPU_V7
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	depends on !ARCH_MULTIPLATFORM
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	help
	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
	  erratum. Any asynchronous access to the L2 cache may encounter a
	  situation in which recent store transactions to the L2 cache are lost
	  and overwritten with stale memory contents from external memory. The
	  workaround disables the write-allocate mode for the L2 cache via the
	  ACTLR register. Note that setting specific bits in the ACTLR register
	  may not be available in non-secure mode.

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config ARM_ERRATA_742230
	bool "ARM errata: DMB operation may be faulty"
	depends on CPU_V7 && SMP
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	depends on !ARCH_MULTIPLATFORM
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	help
	  This option enables the workaround for the 742230 Cortex-A9
	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
	  between two write operations may not ensure the correct visibility
	  ordering of the two writes. This workaround sets a specific bit in
	  the diagnostic register of the Cortex-A9 which causes the DMB
	  instruction to behave as a DSB, ensuring the correct behaviour of
	  the two writes.

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config ARM_ERRATA_742231
	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
	depends on CPU_V7 && SMP
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	depends on !ARCH_MULTIPLATFORM
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	help
	  This option enables the workaround for the 742231 Cortex-A9
	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
	  accessing some data located in the same cache line, may get corrupted
	  data due to bad handling of the address hazard when the line gets
	  replaced from one of the CPUs at the same time as another CPU is
	  accessing it. This workaround sets specific bits in the diagnostic
	  register of the Cortex-A9 which reduces the linefill issuing
	  capabilities of the processor.

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