Commit 028dedba authored by Sudeep Holla's avatar Sudeep Holla Committed by Ionela Voinescu
Browse files

arm64: dts: juno: add mhu doorbell support and scmi device nodes

@Ionela.Voinescu

, later edit: changed compatibility string from
arm,juno-scp-shmem to arm,scmi-shmem
Signed-off-by: Sudeep Holla's avatarSudeep Holla <sudeep.holla@arm.com>
parent ab47a816
......@@ -23,13 +23,14 @@
};
mailbox: mhu@2b1f0000 {
compatible = "arm,mhu", "arm,primecell";
compatible = "arm,mhu-doorbell", "arm,primecell";
reg = <0x0 0x2b1f0000 0x0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mhu_lpri_rx",
"mhu_hpri_rx";
#mbox-cells = <1>;
#mbox-cells = <2>;
mbox-name = "ARM-MHU";
clocks = <&soc_refclk100mhz>;
clock-names = "apb_pclk";
};
......@@ -41,7 +42,7 @@
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#global-interrupts = <1>;
power-domains = <&scpi_devpd 1>;
power-domains = <&scmi_devpd 9>;
dma-coherent;
status = "disabled";
};
......@@ -65,7 +66,7 @@
#iommu-cells = <1>;
#global-interrupts = <1>;
dma-coherent;
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
};
gic: interrupt-controller@2c010000 {
......@@ -125,7 +126,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
in-ports {
port {
......@@ -149,7 +150,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
in-ports {
port {
tpiu_in_port: endpoint {
......@@ -166,7 +167,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
......@@ -203,7 +204,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
arm,scatter-gather;
in-ports {
port {
......@@ -222,7 +223,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
stm_out_port: endpoint {
......@@ -237,7 +238,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
#address-cells = <1>;
......@@ -272,7 +273,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
};
etm0: etm@22040000 {
......@@ -281,7 +282,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
cluster0_etm0_out_port: endpoint {
......@@ -297,7 +298,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
cluster0_funnel_out_port: endpoint {
......@@ -332,7 +333,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
};
etm1: etm@22140000 {
......@@ -341,7 +342,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
cluster0_etm1_out_port: endpoint {
......@@ -357,7 +358,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
};
etm2: etm@23040000 {
......@@ -366,7 +367,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
cluster1_etm0_out_port: endpoint {
......@@ -382,7 +383,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
cluster1_funnel_out_port: endpoint {
......@@ -429,7 +430,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
};
etm3: etm@23140000 {
......@@ -438,7 +439,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
cluster1_etm1_out_port: endpoint {
......@@ -454,7 +455,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
};
etm4: etm@23240000 {
......@@ -463,7 +464,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
cluster1_etm2_out_port: endpoint {
......@@ -479,7 +480,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
};
etm5: etm@23340000 {
......@@ -488,7 +489,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
cluster1_etm3_out_port: endpoint {
......@@ -505,8 +506,8 @@
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&scpi_dvfs 2>;
power-domains = <&scpi_devpd 1>;
clocks = <&scmi_dvfs 2>;
power-domains = <&scmi_devpd 9>;
dma-coherent;
/* The SMMU is only really of interest to bare-metal hypervisors */
/* iommus = <&smmu_gpu 0>; */
......@@ -521,14 +522,24 @@
#size-cells = <1>;
ranges = <0 0x0 0x2e000000 0x8000>;
cpu_scp_lpri: scp-sram@0 {
compatible = "arm,juno-scp-shmem";
reg = <0x0 0x200>;
cpu_scp_lpri0: scp-sram@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x80>;
};
cpu_scp_hpri: scp-sram@200 {
compatible = "arm,juno-scp-shmem";
reg = <0x200 0x200>;
cpu_scp_lpri1: scp-sram@80 {
compatible = "arm,scmi-shmem";
reg = <0x80 0x80>;
};
cpu_scp_hpri0: scp-sram@100 {
compatible = "arm,scmi-shmem";
reg = <0x100 0x80>;
};
cpu_scp_hpri1: scp-sram@180 {
compatible = "arm,scmi-shmem";
reg = <0x180 0x80>;
};
};
......@@ -560,37 +571,37 @@
iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
};
scpi {
compatible = "arm,scpi";
mboxes = <&mailbox 1>;
shmem = <&cpu_scp_hpri>;
firmware {
scmi {
compatible = "arm,scmi";
mbox-names = "tx", "rx";
mboxes = <&mailbox 0 0 &mailbox 0 1>;
shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>;
#address-cells = <1>;
#size-cells = <0>;
clocks {
compatible = "arm,scpi-clocks";
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
};
scpi_dvfs: clocks-0 {
compatible = "arm,scpi-dvfs-clocks";
scmi_dvfs: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
clock-indices = <0>, <1>, <2>;
clock-output-names = "atlclk", "aplclk","gpuclk";
mbox-names = "tx", "rx";
mboxes = <&mailbox 1 0 &mailbox 1 1>;
shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
};
scpi_clk: clocks-1 {
compatible = "arm,scpi-variable-clocks";
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
clock-indices = <3>;
clock-output-names = "pxlclk";
};
};
scpi_devpd: power-controller {
compatible = "arm,scpi-power-domains";
num-domains = <2>;
#power-domain-cells = <1>;
};
scpi_sensors0: sensors {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
scmi_sensors0: protocol@15 {
reg = <0x15>;
#thermal-sensor-cells = <1>;
};
};
};
......@@ -598,40 +609,40 @@
pmic {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 0>;
thermal-sensors = <&scmi_sensors0 0>;
};
soc {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 3>;
thermal-sensors = <&scmi_sensors0 3>;
};
big_cluster_thermal_zone: big-cluster {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 21>;
thermal-sensors = <&scmi_sensors0 21>;
status = "disabled";
};
little_cluster_thermal_zone: little-cluster {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 22>;
thermal-sensors = <&scmi_sensors0 22>;
status = "disabled";
};
gpu0_thermal_zone: gpu0 {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 23>;
thermal-sensors = <&scmi_sensors0 23>;
status = "disabled";
};
gpu1_thermal_zone: gpu1 {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 24>;
thermal-sensors = <&scmi_sensors0 24>;
status = "disabled";
};
};
......@@ -707,7 +718,7 @@
reg = <0 0x7ff50000 0 0x1000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_hdlcd1 0>;
clocks = <&scpi_clk 3>;
clocks = <&scmi_clk 3>;
clock-names = "pxlclk";
port {
......@@ -722,7 +733,7 @@
reg = <0 0x7ff60000 0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_hdlcd0 0>;
clocks = <&scpi_clk 3>;
clocks = <&scmi_clk 3>;
clock-names = "pxlclk";
port {
......
......@@ -6,7 +6,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
csys1_funnel_out_port: endpoint {
......@@ -29,7 +29,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
in-ports {
port {
etf1_in_port: endpoint {
......@@ -52,7 +52,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
power-domains = <&scmi_devpd 8>;
out-ports {
port {
csys2_funnel_out_port: endpoint {
......
......@@ -96,7 +96,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
};
......@@ -113,7 +113,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
};
......@@ -130,7 +130,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
......@@ -147,7 +147,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
......@@ -164,7 +164,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
......@@ -181,7 +181,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
};
......
......@@ -96,7 +96,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <450>;
......@@ -114,7 +114,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <450>;
......@@ -132,7 +132,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <485>;
dynamic-power-coefficient = <140>;
......@@ -150,7 +150,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <485>;
dynamic-power-coefficient = <140>;
......@@ -168,7 +168,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <485>;
dynamic-power-coefficient = <140>;
......@@ -186,7 +186,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <485>;
dynamic-power-coefficient = <140>;
......
......@@ -95,7 +95,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <530>;
......@@ -113,7 +113,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <530>;
......@@ -131,7 +131,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
dynamic-power-coefficient = <140>;
......@@ -149,7 +149,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
dynamic-power-coefficient = <140>;
......@@ -167,7 +167,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
dynamic-power-coefficient = <140>;
......@@ -185,7 +185,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <578>;
dynamic-power-coefficient = <140>;
......
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