1. 13 Nov, 2019 1 commit
  2. 04 Nov, 2019 1 commit
  3. 30 Oct, 2019 2 commits
  4. 28 Oct, 2019 1 commit
  5. 17 Oct, 2019 2 commits
  6. 27 Sep, 2019 1 commit
  7. 25 Sep, 2019 1 commit
  8. 05 Sep, 2019 4 commits
  9. 04 Sep, 2019 3 commits
  10. 01 Sep, 2019 1 commit
  11. 29 Aug, 2019 3 commits
    • Ioana Radulescu's avatar
      dpaa2-eth: Add pause frame support · 8eb3cef8
      Ioana Radulescu authored
      
      
      Starting with firmware version MC10.18.0, we have support for
      L2 flow control. Asymmetrical configuration (Rx or Tx only) is
      supported, but not pause frame autonegotioation.
      
      Pause frame configuration is done via ethtool. By default, we start
      with flow control enabled on both Rx and Tx. Changes are propagated
      to hardware through firmware commands, using two flags (PAUSE,
      ASYM_PAUSE) to specify Rx and Tx pause configuration, as follows:
      
      PAUSE | ASYM_PAUSE | Rx pause | Tx pause
      ----------------------------------------
        0   |     0      | disabled | disabled
        0   |     1      | disabled | enabled
        1   |     0      | enabled  | enabled
        1   |     1      | enabled  | disabled
      
      The hardware can automatically send pause frames when the number
      of buffers in the pool goes below a predefined threshold. Due to
      this, flow control is incompatible with Rx frame queue taildrop
      (both mechanisms target the case when processing of ingress
      frames can't keep up with the Rx rate; for large frames, the number
      of buffers in the pool may never get low enough to trigger pause
      frames as long as taildrop is enabled). So we set pause frame
      generation and Rx FQ taildrop as mutually exclusive.
      
      Signed-off-by: default avatarIoana Radulescu <ruxandra.radulescu@nxp.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8eb3cef8
    • Ioana Radulescu's avatar
      dpaa2-eth: Use stored link settings · cce62943
      Ioana Radulescu authored
      
      
      Whenever a link state change occurs, we get notified and save
      the new link settings in the device's private data. In ethtool
      get_link_ksettings, use the stored state instead of interrogating
      the firmware each time.
      
      Signed-off-by: default avatarIoana Radulescu <ruxandra.radulescu@nxp.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      cce62943
    • Ioana Radulescu's avatar
      dpaa2-eth: Remove support for changing link settings · f7fe7e3d
      Ioana Radulescu authored
      
      
      We only support fixed-link for now, so there is no point in
      offering users the option to change link settings via ethtool.
      
      Functionally there is no change, since firmware prevents us from
      changing link parameters anyway.
      
      Signed-off-by: default avatarIoana Radulescu <ruxandra.radulescu@nxp.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f7fe7e3d
  12. 22 Aug, 2019 2 commits
  13. 21 Aug, 2019 1 commit
  14. 10 Aug, 2019 1 commit
  15. 09 Aug, 2019 1 commit
  16. 03 Aug, 2019 4 commits
    • Claudiu Manoil's avatar
      enetc: Add mdio bus driver for the PCIe MDIO endpoint · 231ece36
      Claudiu Manoil authored
      
      
      ENETC ports can manage the MDIO bus via local register
      interface.  However there's also a centralized way
      to manage the MDIO bus, via the MDIO PCIe endpoint
      device integrated by the same root complex that also
      integrates the ENETC ports (eth controllers).
      
      Depending on board design and use case, centralized
      access to MDIO may be better than using local ENETC
      port registers.  For instance, on the LS1028A QDS board
      where MDIO muxing is required.  Also, the LS1028A on-chip
      switch doesn't have a local MDIO register interface.
      
      The current patch registers the above PCIe endpoint as a
      separate MDIO bus and provides a driver for it by re-using
      the code used for local MDIO access.  It also allows the
      ENETC port PHYs to be managed by this driver if the local
      "mdio" node is missing from the ENETC port node.
      
      Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      231ece36
    • Claudiu Manoil's avatar
      enetc: Clean up makefile · 0c010a9d
      Claudiu Manoil authored
      
      
      Clean up overcomplicated makefile to make it more maintainable.
      Basically, there's a set of common objects shared between
      the PF and VF driver modules.  This can be implemented in a
      simpler way, without conditionals, less repetition, allowing
      also for easier updates in the future.
      
      Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      0c010a9d
    • Claudiu Manoil's avatar
      enetc: Clean up local mdio bus allocation · 2152e7a2
      Claudiu Manoil authored
      What's needed is basically a pointer to the mdio registers.
      This is one way to store it inside bus->priv allocated space,
      without upsetting sparse.
      Reworked accessors to avoid __iomem casting.
      Used devm_* variant to further clean up the init error /
      remove paths.
      
      Fixes following sparse warning:
       warning: incorrect type in assignment (different address spaces)
          expected void *priv
          got struct enetc_mdio_regs [noderef] <asn:2>*[assigned] regs
      
      Fixes: ebfcb23d
      
       ("enetc: Add ENETC PF level external MDIO support")
      
      Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2152e7a2
    • YueHaibing's avatar
      enetc: Select PHYLIB while CONFIG_FSL_ENETC_VF is set · 2802d2cf
      YueHaibing authored
      
      
      Like FSL_ENETC, when CONFIG_FSL_ENETC_VF is set,
      we should select PHYLIB, otherwise building still fails:
      
      drivers/net/ethernet/freescale/enetc/enetc.o: In function `enetc_open':
      enetc.c:(.text+0x2744): undefined reference to `phy_start'
      enetc.c:(.text+0x282c): undefined reference to `phy_disconnect'
      drivers/net/ethernet/freescale/enetc/enetc.o: In function `enetc_close':
      enetc.c:(.text+0x28f8): undefined reference to `phy_stop'
      enetc.c:(.text+0x2904): undefined reference to `phy_disconnect'
      drivers/net/ethernet/freescale/enetc/enetc_ethtool.o:(.rodata+0x3f8): undefined reference to `phy_ethtool_get_link_ksettings'
      drivers/net/ethernet/freescale/enetc/enetc_ethtool.o:(.rodata+0x400): undefined reference to `phy_ethtool_set_link_ksettings'
      
      Reported-by: default avatarHulk Robot <hulkci@huawei.com>
      Fixes: d4fd0404
      
       ("enetc: Introduce basic PF and VF ENETC ethernet drivers")
      Signed-off-by: default avatarYueHaibing <yuehaibing@huawei.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2802d2cf
  17. 30 Jul, 2019 2 commits
  18. 25 Jul, 2019 1 commit
  19. 24 Jul, 2019 1 commit
  20. 23 Jul, 2019 1 commit
  21. 15 Jul, 2019 1 commit
  22. 15 Jun, 2019 2 commits
  23. 12 Jun, 2019 3 commits