Commit bc727213 authored by Jean-Philippe Brucker's avatar Jean-Philippe Brucker Committed by Robin Murphy
Browse files

dt-bindings: Add SMMUv3 PMCG binding



Add binding for the SMMUv3 PMU. Each node represents a PMCG, and is placed
as a sibling node of the SMMU. As PMCGs are mainly implementation
defined there is no 1-1 relation between SMMU and PMCG. The SMMU could
have PMU counters for the TCU and each TBU, or a single PMCG.

TODO: although the Linux implementation doesn't need them, it'd be nice
to have links from the PMCG node to its associated SMMU. IORT does offer
this (Node reference) and perhaps it could later help users figure out
which PMCG is which on systems with dozens of SMMU.

Signed-off-by: default avatarJean-Philippe Brucker <jean-philippe@linaro.org>
[rm: move to /perf, tweak properties, add MMU-600 compatible ]
Signed-off-by: Robin Murphy's avatarRobin Murphy <robin.murphy@arm.com>
parent fa55b7dc
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM SMMUv3 Performance Monitor Counter Group
maintainers:
- Will Deacon <will@kernel.org>
- Robin Murphy <robin.murphy@arm.com>
description:
An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
They are standalone performance monitoring units that support both
architected and IMPLEMENTATION DEFINED event counters.
properties:
$nodename:
pattern: "^pmu@[0-9a-f]*"
compatible:
oneOf:
- items:
- const: arm,mmu-600-pmcg
- const: arm,smmu-v3-pmcg
- const: arm,smmu-v3-pmcg
reg:
minItems: 1
maxItems: 2
items:
- description: Register page 0
- description: Register page 1, if PMCR.RELOC_CTRS = 1
interrupts:
maxItems: 1
msi-parent: true
required:
- compatible
- reg
- anyOf:
- interrupts
- msi-parent
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
tcu: pmu@2b420000 {
compatible = "arm,smmu-v3-pmcg";
reg = <0 0x2b420000 0 0x1000>,
<0 0x2b430000 0 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
msi-parent = <&its 0xff0000>;
};
tbu0: pmu@2b440000 {
compatible = "arm,smmu-v3-pmcg";
reg = <0 0x2b440000 0 0x1000>,
<0 0x2b450000 0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
msi-parent = <&its 0xff0000>;
};
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