am4372.dtsi 28.2 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
/*
 * Device Tree Source for AM4372 SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

11
#include <dt-bindings/gpio/gpio.h>
12
13
14
15
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "ti,am4372", "ti,am43";
16
	interrupt-parent = <&wakeupgen>;
17
18
	#address-cells = <1>;
	#size-cells = <1>;
19

20
21
22
23
	memory {
		device_type = "memory";
		reg = <0 0>;
	};
24
25

	aliases {
26
27
28
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
29
		serial0 = &uart0;
30
31
32
33
34
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
35
36
		ethernet0 = &cpsw_emac0;
		ethernet1 = &cpsw_emac1;
37
		spi0 = &qspi;
38
39
40
	};

	cpus {
41
42
		#address-cells = <1>;
		#size-cells = <0>;
43
		cpu: cpu@0 {
44
			compatible = "arm,cortex-a9";
45
46
			device_type = "cpu";
			reg = <0>;
47
48
49
50

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

51
52
53
54
			operating-points-v2 = <&cpu0_opp_table>;
			ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>;
			ti,syscon-rev = <&scm_conf 0x600>;

55
			clock-latency = <300000>; /* From omap-cpufreq driver */
56
57
58
		};
	};

59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
	cpu0_opp_table: opp_table0 {
		compatible = "operating-points-v2";

		opp50@300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <950000 931000 969000>;
			opp-supported-hw = <0xFF 0x01>;
			opp-suspend;
		};

		opp100@600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1100000 1078000 1122000>;
			opp-supported-hw = <0xFF 0x04>;
		};

		opp120@720000000 {
			opp-hz = /bits/ 64 <720000000>;
			opp-microvolt = <1200000 1176000 1224000>;
			opp-supported-hw = <0xFF 0x08>;
		};

		oppturbo@800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <1260000 1234800 1285200>;
			opp-supported-hw = <0xFF 0x10>;
		};

		oppnitro@1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <1325000 1298500 1351500>;
			opp-supported-hw = <0xFF 0x20>;
		};
	};

94
95
96
97
98
99
	gic: interrupt-controller@48241000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48241000 0x1000>,
		      <0x48240100 0x0100>;
100
101
102
103
104
105
106
107
108
		interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
		compatible = "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48281000 0x1000>;
		interrupt-parent = <&gic>;
109
110
	};

111
112
113
114
115
116
117
118
	scu: scu@48240000 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x48240000 0x100>;
	};

	global_timer: timer@48240200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x48240200 0x100>;
119
		interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
120
		interrupt-parent = <&gic>;
121
		clocks = <&mpu_periphclk>;
122
123
124
125
126
	};

	local_timer: timer@48240600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x48240600 0x100>;
127
		interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
128
		interrupt-parent = <&gic>;
129
		clocks = <&mpu_periphclk>;
130
131
	};

132
133
134
135
136
137
138
	l2-cache-controller@48242000 {
		compatible = "arm,pl310-cache";
		reg = <0x48242000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

139
	ocp@44000000 {
140
		compatible = "ti,am4372-l3-noc", "simple-bus";
141
142
143
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
144
		ti,hwmods = "l3_main";
145
146
147
148
		reg = <0x44000000 0x400000
		       0x44800000 0x400000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
149

150
151
152
153
154
		l4_wkup: l4_wkup@44c00000 {
			compatible = "ti,am4-l4-wkup", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x44c00000 0x287000>;
Tero Kristo's avatar
Tero Kristo committed
155

156
157
158
159
160
161
162
163
164
			wkup_m3: wkup_m3@100000 {
				compatible = "ti,am4372-wkup-m3";
				reg = <0x100000 0x4000>,
				      <0x180000	0x2000>;
				reg-names = "umem", "dmem";
				ti,hwmods = "wkup_m3";
				ti,pm-firmware = "am335x-pm-firmware.elf";
			};

165
166
167
			prcm: prcm@1f0000 {
				compatible = "ti,am4-prcm";
				reg = <0x1f0000 0x11000>;
Keerthy's avatar
Keerthy committed
168
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
Tero Kristo's avatar
Tero Kristo committed
169

170
171
172
173
				prcm_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};
Tero Kristo's avatar
Tero Kristo committed
174

175
176
				prcm_clockdomains: clockdomains {
				};
Tero Kristo's avatar
Tero Kristo committed
177
178
			};

179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
			scm: scm@210000 {
				compatible = "ti,am4-scm", "simple-bus";
				reg = <0x210000 0x4000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x210000 0x4000>;

				am43xx_pinmux: pinmux@800 {
					compatible = "ti,am437-padconf",
						     "pinctrl-single";
					reg = <0x800 0x31c>;
					#address-cells = <1>;
					#size-cells = <0>;
					#interrupt-cells = <1>;
					interrupt-controller;
					pinctrl-single,register-width = <32>;
					pinctrl-single,function-mask = <0xffffffff>;
				};

				scm_conf: scm_conf@0 {
					compatible = "syscon";
					reg = <0x0 0x800>;
					#address-cells = <1>;
					#size-cells = <1>;

					scm_clocks: clocks {
						#address-cells = <1>;
						#size-cells = <0>;
					};
				};

210
211
212
213
214
215
216
217
				wkup_m3_ipc: wkup_m3_ipc@1324 {
					compatible = "ti,am4372-wkup-m3-ipc";
					reg = <0x1324 0x44>;
					interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
					ti,rproc = <&wkup_m3>;
					mboxes = <&mailbox &mbox_wkupm3>;
				};

218
219
220
221
222
223
224
225
				edma_xbar: dma-router@f90 {
					compatible = "ti,am335x-edma-crossbar";
					reg = <0xf90 0x40>;
					#dma-cells = <3>;
					dma-requests = <64>;
					dma-masters = <&edma>;
				};

226
227
				scm_clockdomains: clockdomains {
				};
Tero Kristo's avatar
Tero Kristo committed
228
229
230
			};
		};

Dave Gerlach's avatar
Dave Gerlach committed
231
232
233
234
235
236
		emif: emif@4c000000 {
			compatible = "ti,emif-am4372";
			reg = <0x4c000000 0x1000000>;
			ti,hwmods = "emif";
		};

237
		edma: edma@49000000 {
238
239
240
241
			compatible = "ti,edma3-tpcc";
			ti,hwmods = "tpcc";
			reg =	<0x49000000 0x10000>;
			reg-names = "edma3_cc";
242
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
243
244
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
245
			interrupt-names = "edma3_ccint", "edma3_mperr",
246
247
248
249
250
251
252
					  "edma3_ccerrint";
			dma-requests = <64>;
			#dma-cells = <2>;

			ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
				   <&edma_tptc2 0>;

253
			ti,edma-memcpy-channels = <58 59>;
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
		};

		edma_tptc0: tptc@49800000 {
			compatible = "ti,edma3-tptc";
			ti,hwmods = "tptc0";
			reg =	<0x49800000 0x100000>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma3_tcerrint";
		};

		edma_tptc1: tptc@49900000 {
			compatible = "ti,edma3-tptc";
			ti,hwmods = "tptc1";
			reg =	<0x49900000 0x100000>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma3_tcerrint";
		};

		edma_tptc2: tptc@49a00000 {
			compatible = "ti,edma3-tptc";
			ti,hwmods = "tptc2";
			reg =	<0x49a00000 0x100000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma3_tcerrint";
278
		};
279
280
281
282
283

		uart0: serial@44e09000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x44e09000 0x2000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
			ti,hwmods = "uart1";
		};

		uart1: serial@48022000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48022000 0x2000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart2";
			status = "disabled";
		};

		uart2: serial@48024000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48024000 0x2000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart3";
			status = "disabled";
		};

		uart3: serial@481a6000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a6000 0x2000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart4";
			status = "disabled";
		};

		uart4: serial@481a8000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a8000 0x2000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart5";
			status = "disabled";
		};

		uart5: serial@481aa000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481aa000 0x2000>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart6";
			status = "disabled";
325
326
		};

327
328
329
330
331
		mailbox: mailbox@480C8000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x480C8000 0x200>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mailbox";
332
			#mbox-cells = <1>;
333
334
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <8>;
335
			mbox_wkupm3: wkup_m3 {
336
				ti,mbox-send-noirq;
337
338
339
				ti,mbox-tx = <0 0 0>;
				ti,mbox-rx = <0 0 3>;
			};
340
341
		};

342
343
344
345
346
		timer1: timer@44e31000 {
			compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
			reg = <0x44e31000 0x400>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-alwon;
347
			ti,hwmods = "timer1";
348
349
350
351
352
353
		};

		timer2: timer@48040000  {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48040000  0x400>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
			ti,hwmods = "timer2";
		};

		timer3: timer@48042000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48042000 0x400>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer3";
			status = "disabled";
		};

		timer4: timer@48044000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48044000 0x400>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer4";
			status = "disabled";
		};

		timer5: timer@48046000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48046000 0x400>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer5";
			status = "disabled";
		};

		timer6: timer@48048000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48048000 0x400>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer6";
			status = "disabled";
		};

		timer7: timer@4804a000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4804a000 0x400>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer7";
			status = "disabled";
		};

		timer8: timer@481c1000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x481c1000 0x400>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer8";
			status = "disabled";
		};

		timer9: timer@4833d000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833d000 0x400>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer9";
			status = "disabled";
		};

		timer10: timer@4833f000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833f000 0x400>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer10";
			status = "disabled";
		};

		timer11: timer@48341000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48341000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer11";
			status = "disabled";
431
432
433
434
435
		};

		counter32k: counter@44e86000 {
			compatible = "ti,am4372-counter32k","ti,omap-counter32k";
			reg = <0x44e86000 0x40>;
436
437
438
			ti,hwmods = "counter_32k";
		};

439
		rtc: rtc@44e3e000 {
440
441
			compatible = "ti,am4372-rtc", "ti,am3352-rtc",
				     "ti,da830-rtc";
442
443
444
445
			reg = <0x44e3e000 0x1000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "rtc";
446
447
			clocks = <&clk_32768_ck>;
			clock-names = "int-clk";
448
449
450
			status = "disabled";
		};

451
		wdt: wdt@44e35000 {
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
			compatible = "ti,am4372-wdt","ti,omap3-wdt";
			reg = <0x44e35000 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "wd_timer2";
		};

		gpio0: gpio@44e07000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x44e07000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio1";
			status = "disabled";
		};

		gpio1: gpio@4804c000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x4804c000 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio2";
			status = "disabled";
		};

		gpio2: gpio@481ac000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ac000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio3";
			status = "disabled";
		};

		gpio3: gpio@481ae000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ae000 0x1000>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio4";
			status = "disabled";
		};

		gpio4: gpio@48320000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48320000 0x1000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio5";
			status = "disabled";
		};

		gpio5: gpio@48322000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48322000 0x1000>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio6";
			status = "disabled";
		};

530
531
532
533
534
535
536
		hwspinlock: spinlock@480ca000 {
			compatible = "ti,omap4-hwspinlock";
			reg = <0x480ca000 0x1000>;
			ti,hwmods = "spinlock";
			#hwlock-cells = <1>;
		};

537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
		i2c0: i2c@44e0b000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x44e0b000 0x1000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@4802a000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4802a000 0x1000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@4819c000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4819c000 0x1000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi0: spi@48030000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48030000 0x400>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi0";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

577
578
579
580
581
582
		mmc1: mmc@48060000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x48060000 0x1000>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
583
584
			dmas = <&edma 24 0>,
				<&edma 25 0>;
585
586
587
588
589
590
591
592
593
594
			dma-names = "tx", "rx";
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		mmc2: mmc@481d8000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x481d8000 0x1000>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
595
596
			dmas = <&edma 2 0>,
				<&edma 3 0>;
597
598
599
600
601
602
603
604
605
606
607
608
609
610
			dma-names = "tx", "rx";
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		mmc3: mmc@47810000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x47810000 0x1000>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
		spi1: spi@481a0000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a0000 0x400>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@481a2000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a2000 0x400>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi3: spi@481a4000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a4000 0x400>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi4: spi@48345000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48345000 0x400>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi4";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mac: ethernet@4a100000 {
			compatible = "ti,am4372-cpsw","ti,cpsw";
			reg = <0x4a100000 0x800
			       0x4a101200 0x100>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
659
660
			#address-cells = <1>;
			#size-cells = <1>;
661
			ti,hwmods = "cpgmac0";
662
663
664
665
666
			clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
				 <&dpll_clksel_mac_clk>;
			clock-names = "fck", "cpts", "50mclk";
			assigned-clocks = <&dpll_clksel_mac_clk>;
			assigned-clock-rates = <50000000>;
667
			status = "disabled";
668
669
670
671
672
673
674
675
676
677
			cpdma_channels = <8>;
			ale_entries = <1024>;
			bd_ram_size = <0x2000>;
			no_bd_ram = <0>;
			mac_control = <0x20>;
			slaves = <2>;
			active_slave = <0>;
			cpts_clock_mult = <0x80000000>;
			cpts_clock_shift = <29>;
			ranges;
678
			syscon = <&scm_conf>;
679
680

			davinci_mdio: mdio@4a101000 {
681
				compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
				reg = <0x4a101000 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;
				ti,hwmods = "davinci_mdio";
				bus_freq = <1000000>;
				status = "disabled";
			};

			cpsw_emac0: slave@4a100200 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};

			cpsw_emac1: slave@4a100300 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};
699
700
701
702
703
704

			phy_sel: cpsw-phy-sel@44e10650 {
				compatible = "ti,am43xx-cpsw-phy-sel";
				reg= <0x44e10650 0x4>;
				reg-names = "gmii-sel";
			};
705
706
707
708
709
		};

		epwmss0: epwmss@48300000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48300000 0x10>;
710
711
712
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
713
714
			ti,hwmods = "epwmss0";
			status = "disabled";
715
716

			ecap0: ecap@48300100 {
717
718
719
				compatible = "ti,am4372-ecap",
					     "ti,am3352-ecap",
					     "ti,am33xx-ecap";
720
				#pwm-cells = <3>;
721
				reg = <0x48300100 0x80>;
722
723
				clocks = <&l4ls_gclk>;
				clock-names = "fck";
724
725
726
				status = "disabled";
			};

727
			ehrpwm0: pwm@48300200 {
728
729
730
				compatible = "ti,am4372-ehrpwm",
					     "ti,am3352-ehrpwm",
					     "ti,am33xx-ehrpwm";
731
				#pwm-cells = <3>;
732
				reg = <0x48300200 0x80>;
733
734
				clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
				clock-names = "tbclk", "fck";
735
736
				status = "disabled";
			};
737
738
739
740
741
		};

		epwmss1: epwmss@48302000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48302000 0x10>;
742
743
744
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
745
746
			ti,hwmods = "epwmss1";
			status = "disabled";
747
748

			ecap1: ecap@48302100 {
749
750
751
				compatible = "ti,am4372-ecap",
					     "ti,am3352-ecap",
					     "ti,am33xx-ecap";
752
				#pwm-cells = <3>;
753
				reg = <0x48302100 0x80>;
754
755
				clocks = <&l4ls_gclk>;
				clock-names = "fck";
756
757
758
				status = "disabled";
			};

759
			ehrpwm1: pwm@48302200 {
760
761
762
				compatible = "ti,am4372-ehrpwm",
					     "ti,am3352-ehrpwm",
					     "ti,am33xx-ehrpwm";
763
				#pwm-cells = <3>;
764
				reg = <0x48302200 0x80>;
765
766
				clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
				clock-names = "tbclk", "fck";
767
768
				status = "disabled";
			};
769
770
771
772
773
		};

		epwmss2: epwmss@48304000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48304000 0x10>;
774
775
776
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
777
778
			ti,hwmods = "epwmss2";
			status = "disabled";
779
780

			ecap2: ecap@48304100 {
781
782
783
				compatible = "ti,am4372-ecap",
					     "ti,am3352-ecap",
					     "ti,am33xx-ecap";
784
				#pwm-cells = <3>;
785
				reg = <0x48304100 0x80>;
786
787
				clocks = <&l4ls_gclk>;
				clock-names = "fck";
788
789
790
				status = "disabled";
			};

791
			ehrpwm2: pwm@48304200 {
792
793
794
				compatible = "ti,am4372-ehrpwm",
					     "ti,am3352-ehrpwm",
					     "ti,am33xx-ehrpwm";
795
				#pwm-cells = <3>;
796
				reg = <0x48304200 0x80>;
797
798
				clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
				clock-names = "tbclk", "fck";
799
800
				status = "disabled";
			};
801
802
803
804
805
		};

		epwmss3: epwmss@48306000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48306000 0x10>;
806
807
808
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
809
810
			ti,hwmods = "epwmss3";
			status = "disabled";
811

812
			ehrpwm3: pwm@48306200 {
813
814
815
				compatible = "ti,am4372-ehrpwm",
					     "ti,am3352-ehrpwm",
					     "ti,am33xx-ehrpwm";
816
				#pwm-cells = <3>;
817
				reg = <0x48306200 0x80>;
818
819
				clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
				clock-names = "tbclk", "fck";
820
821
				status = "disabled";
			};
822
823
824
825
826
		};

		epwmss4: epwmss@48308000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48308000 0x10>;
827
828
829
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
830
831
			ti,hwmods = "epwmss4";
			status = "disabled";
832

833
			ehrpwm4: pwm@48308200 {
834
835
836
				compatible = "ti,am4372-ehrpwm",
					     "ti,am3352-ehrpwm",
					     "ti,am33xx-ehrpwm";
837
				#pwm-cells = <3>;
838
				reg = <0x48308200 0x80>;
839
840
				clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
				clock-names = "tbclk", "fck";
841
842
				status = "disabled";
			};
843
844
845
846
847
		};

		epwmss5: epwmss@4830a000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x4830a000 0x10>;
848
849
850
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
851
852
			ti,hwmods = "epwmss5";
			status = "disabled";
853

854
			ehrpwm5: pwm@4830a200 {
855
856
857
				compatible = "ti,am4372-ehrpwm",
					     "ti,am3352-ehrpwm",
					     "ti,am33xx-ehrpwm";
858
				#pwm-cells = <3>;
859
				reg = <0x4830a200 0x80>;
860
861
				clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
				clock-names = "tbclk", "fck";
862
863
864
865
				status = "disabled";
			};
		};

866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
		tscadc: tscadc@44e0d000 {
			compatible = "ti,am3359-tscadc";
			reg = <0x44e0d000 0x1000>;
			ti,hwmods = "adc_tsc";
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&adc_tsc_fck>;
			clock-names = "fck";
			status = "disabled";

			tsc {
				compatible = "ti,am3359-tsc";
			};

			adc {
				#io-channel-cells = <1>;
				compatible = "ti,am3359-adc";
			};

		};

886
887
888
889
		sham: sham@53100000 {
			compatible = "ti,omap5-sham";
			ti,hwmods = "sham";
			reg = <0x53100000 0x300>;
890
			dmas = <&edma 36 0>;
891
892
			dma-names = "rx";
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
893
		};
894
895
896
897
898
899

		aes: aes@53501000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes";
			reg = <0x53501000 0xa0>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
900
901
			dmas = <&edma 6 0>,
				<&edma 5 0>;
902
			dma-names = "tx", "rx";
903
		};
904
905
906
907
908
909

		des: des@53701000 {
			compatible = "ti,omap4-des";
			ti,hwmods = "des";
			reg = <0x53701000 0xa0>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
910
911
			dmas = <&edma 34 0>,
				<&edma 33 0>;
912
			dma-names = "tx", "rx";
913
		};
914

915
916
917
918
919
920
921
		rng: rng@48310000 {
			compatible = "ti,omap4-rng";
			ti,hwmods = "rng";
			reg = <0x48310000 0x2000>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
		};

922
923
924
925
926
927
928
		mcasp0: mcasp@48038000 {
			compatible = "ti,am33xx-mcasp-audio";
			ti,hwmods = "mcasp0";
			reg = <0x48038000 0x2000>,
			      <0x46000000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <80>, <81>;
929
			interrupt-names = "tx", "rx";
930
			status = "disabled";
931
932
			dmas = <&edma 8 2>,
			       <&edma 9 2>;
933
934
935
936
937
938
939
940
941
942
			dma-names = "tx", "rx";
		};

		mcasp1: mcasp@4803C000 {
			compatible = "ti,am33xx-mcasp-audio";
			ti,hwmods = "mcasp1";
			reg = <0x4803C000 0x2000>,
			      <0x46400000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <82>, <83>;
943
			interrupt-names = "tx", "rx";
944
			status = "disabled";
945
946
			dmas = <&edma 10 2>,
			       <&edma 11 2>;
947
948
			dma-names = "tx", "rx";
		};
949
950
951
952
953
954
955
956
957
958
959
960
961
962

		elm: elm@48080000 {
			compatible = "ti,am3352-elm";
			reg = <0x48080000 0x2000>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "elm";
			clocks = <&l4ls_gclk>;
			clock-names = "fck";
			status = "disabled";
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,am3352-gpmc";
			ti,hwmods = "gpmc";
963
			dmas = <&edma 52 0>;
964
			dma-names = "rxtx";
965
966
967
968
969
970
971
972
			clocks = <&l3s_gclk>;
			clock-names = "fck";
			reg = <0x50000000 0x2000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			gpmc,num-cs = <7>;
			gpmc,num-waitpins = <2>;
			#address-cells = <2>;
			#size-cells = <1>;
973
974
			interrupt-controller;
			#interrupt-cells = <2>;
975
976
			gpio-controller;
			#gpio-cells = <2>;
977
978
			status = "disabled";
		};
979
980

		ocp2scp0: ocp2scp@483a8000 {
981
			compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
982
983
984
985
986
987
988
989
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "ocp2scp0";

			usb2_phy1: phy@483a8000 {
				compatible = "ti,am437x-usb2";
				reg = <0x483a8000 0x8000>;
990
				syscon-phy-power = <&scm_conf 0x620>;
991
992
993
994
995
996
997
998
999
				clocks = <&usb_phy0_always_on_clk32k>,
					 <&usb_otg_ss0_refclk960m>;
				clock-names = "wkupclk", "refclk";
				#phy-cells = <0>;
				status = "disabled";
			};
		};

		ocp2scp1: ocp2scp@483e8000 {
1000
			compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
1001
1002
1003
1004
1005
1006
1007
1008
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "ocp2scp1";

			usb2_phy2: phy@483e8000 {
				compatible = "ti,am437x-usb2";
				reg = <0x483e8000 0x8000>;
1009
				syscon-phy-power = <&scm_conf 0x628>;
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
				clocks = <&usb_phy1_always_on_clk32k>,
					 <&usb_otg_ss1_refclk960m>;
				clock-names = "wkupclk", "refclk";
				#phy-cells = <0>;
				status = "disabled";
			};
		};

		dwc3_1: omap_dwc3@48380000 {
			compatible = "ti,am437x-dwc3";
			ti,hwmods = "usb_otg_ss0";
			reg = <0x48380000 0x10000>;
			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <1>;
			ranges;

			usb1: usb@48390000 {
				compatible = "synopsys,dwc3";
1030
				reg = <0x48390000 0x10000>;
1031
1032
1033
1034
1035
1036
				interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "peripheral",
						  "host",
						  "otg";
1037
1038
1039
1040
1041
				phys = <&usb2_phy1>;
				phy-names = "usb2-phy";
				maximum-speed = "high-speed";
				dr_mode = "otg";
				status = "disabled";
1042
1043
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
			};
		};

		dwc3_2: omap_dwc3@483c0000 {
			compatible = "ti,am437x-dwc3";
			ti,hwmods = "usb_otg_ss1";
			reg = <0x483c0000 0x10000>;
			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <1>;
			ranges;

			usb2: usb@483d0000 {
				compatible = "synopsys,dwc3";
1059
				reg = <0x483d0000 0x10000>;
1060
1061
1062
1063
1064
1065
				interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "peripheral",
						  "host",
						  "otg";
1066
1067
1068
1069
1070
				phys = <&usb2_phy2>;
				phy-names = "usb2-phy";
				maximum-speed = "high-speed";
				dr_mode = "otg";
				status = "disabled";
1071
1072
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
1073
1074
			};
		};
1075
1076
1077

		qspi: qspi@47900000 {
			compatible = "ti,am4372-qspi";
1078
1079
1080
			reg = <0x47900000 0x100>,
			      <0x30000000 0x4000000>;
			reg-names = "qspi_base", "qspi_mmap";
1081
1082
1083
1084
1085
1086
1087
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "qspi";
			interrupts = <0 138 0x4>;
			num-cs = <4>;
			status = "disabled";
		};
1088
1089

		hdq: hdq@48347000 {
1090
			compatible = "ti,am4372-hdq";
1091
1092
1093
1094
1095
1096
1097
			reg = <0x48347000 0x1000>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&func_12m_clk>;
			clock-names = "fck";
			ti,hwmods = "hdq1w";
			status = "disabled";
		};
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109

		dss: dss@4832a000 {
			compatible = "ti,omap3-dss";
			reg = <0x4832a000 0x200>;
			status = "disabled";
			ti,hwmods = "dss_core";
			clocks = <&disp_clk>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

1110
			dispc: dispc@4832a400 {
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
				compatible = "ti,omap3-dispc";
				reg = <0x4832a400 0x400>;
				interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
				ti,hwmods = "dss_dispc";
				clocks = <&disp_clk>;
				clock-names = "fck";
			};

			rfbi: rfbi@4832a800 {
				compatible = "ti,omap3-rfbi";
				reg = <0x4832a800 0x100>;
				ti,hwmods = "dss_rfbi";
				clocks = <&disp_clk>;
				clock-names = "fck";
1125
				status = "disabled";
1126
1127
			};
		};
1128
1129
1130
1131
1132

		ocmcram: ocmcram@40300000 {
			compatible = "mmio-sram";
			reg = <0x40300000 0x40000>; /* 256k */
		};
1133
1134
1135
1136
1137
1138
1139

		dcan0: can@481cc000 {
			compatible = "ti,am4372-d_can", "ti,am3352-d_can";
			ti,hwmods = "d_can0";
			clocks = <&dcan0_fck>;
			clock-names = "fck";
			reg = <0x481cc000 0x2000>;
1140
			syscon-raminit = <&scm_conf 0x644 0>;
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		dcan1: can@481d0000 {
			compatible = "ti,am4372-d_can", "ti,am3352-d_can";
			ti,hwmods = "d_can1";
			clocks = <&dcan1_fck>;
			clock-names = "fck";
			reg = <0x481d0000 0x2000>;
1151
			syscon-raminit = <&scm_conf 0x644 1>;
1152
1153
1154
			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170

		vpfe0: vpfe@48326000 {
			compatible = "ti,am437x-vpfe";
			reg = <0x48326000 0x2000>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "vpfe0";
			status = "disabled";
		};

		vpfe1: vpfe@48328000 {
			compatible = "ti,am437x-vpfe";
			reg = <0x48328000 0x2000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "vpfe1";
			status = "disabled";
		};
1171
1172
	};
};
Tero Kristo's avatar
Tero Kristo committed
1173
1174

/include/ "am43xx-clocks.dtsi"