am4372.dtsi 24.5 KB
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/*
 * Device Tree Source for AM4372 SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,am4372", "ti,am43";
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	interrupt-parent = <&wakeupgen>;
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	aliases {
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		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
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		serial0 = &uart0;
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		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
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		ethernet0 = &cpsw_emac0;
		ethernet1 = &cpsw_emac1;
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	};

	cpus {
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		#address-cells = <1>;
		#size-cells = <0>;
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		cpu: cpu@0 {
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			compatible = "arm,cortex-a9";
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			device_type = "cpu";
			reg = <0>;
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			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */
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		};
	};

	gic: interrupt-controller@48241000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48241000 0x1000>,
		      <0x48240100 0x0100>;
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		interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
		compatible = "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48281000 0x1000>;
		interrupt-parent = <&gic>;
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	};

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	l2-cache-controller@48242000 {
		compatible = "arm,pl310-cache";
		reg = <0x48242000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

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	ocp {
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		compatible = "ti,am4372-l3-noc", "simple-bus";
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		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
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		ti,hwmods = "l3_main";
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		reg = <0x44000000 0x400000
		       0x44800000 0x400000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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		l4_wkup: l4_wkup@44c00000 {
			compatible = "ti,am4-l4-wkup", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x44c00000 0x287000>;
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			wkup_m3: wkup_m3@100000 {
				compatible = "ti,am4372-wkup-m3";
				reg = <0x100000 0x4000>,
				      <0x180000	0x2000>;
				reg-names = "umem", "dmem";
				ti,hwmods = "wkup_m3";
				ti,pm-firmware = "am335x-pm-firmware.elf";
			};

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			prcm: prcm@1f0000 {
				compatible = "ti,am4-prcm";
				reg = <0x1f0000 0x11000>;
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				prcm_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};
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				prcm_clockdomains: clockdomains {
				};
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			};

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			scm: scm@210000 {
				compatible = "ti,am4-scm", "simple-bus";
				reg = <0x210000 0x4000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x210000 0x4000>;

				am43xx_pinmux: pinmux@800 {
					compatible = "ti,am437-padconf",
						     "pinctrl-single";
					reg = <0x800 0x31c>;
					#address-cells = <1>;
					#size-cells = <0>;
					#interrupt-cells = <1>;
					interrupt-controller;
					pinctrl-single,register-width = <32>;
					pinctrl-single,function-mask = <0xffffffff>;
				};

				scm_conf: scm_conf@0 {
					compatible = "syscon";
					reg = <0x0 0x800>;
					#address-cells = <1>;
					#size-cells = <1>;

					scm_clocks: clocks {
						#address-cells = <1>;
						#size-cells = <0>;
					};
				};

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				wkup_m3_ipc: wkup_m3_ipc@1324 {
					compatible = "ti,am4372-wkup-m3-ipc";
					reg = <0x1324 0x44>;
					interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
					ti,rproc = <&wkup_m3>;
					mboxes = <&mailbox &mbox_wkupm3>;
				};

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				scm_clockdomains: clockdomains {
				};
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			};
		};

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		emif: emif@4c000000 {
			compatible = "ti,emif-am4372";
			reg = <0x4c000000 0x1000000>;
			ti,hwmods = "emif";
		};

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		edma: edma@49000000 {
			compatible = "ti,edma3";
			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
			reg =	<0x49000000 0x10000>,
				<0x44e10f90 0x10>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
		};
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		uart0: serial@44e09000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x44e09000 0x2000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "uart1";
		};

		uart1: serial@48022000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48022000 0x2000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart2";
			status = "disabled";
		};

		uart2: serial@48024000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x48024000 0x2000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart3";
			status = "disabled";
		};

		uart3: serial@481a6000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a6000 0x2000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart4";
			status = "disabled";
		};

		uart4: serial@481a8000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481a8000 0x2000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart5";
			status = "disabled";
		};

		uart5: serial@481aa000 {
			compatible = "ti,am4372-uart","ti,omap2-uart";
			reg = <0x481aa000 0x2000>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "uart6";
			status = "disabled";
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		};

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		mailbox: mailbox@480C8000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x480C8000 0x200>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "mailbox";
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			#mbox-cells = <1>;
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			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <8>;
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			mbox_wkupm3: wkup_m3 {
				ti,mbox-tx = <0 0 0>;
				ti,mbox-rx = <0 0 3>;
			};
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		};

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		timer1: timer@44e31000 {
			compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
			reg = <0x44e31000 0x400>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-alwon;
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			ti,hwmods = "timer1";
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		};

		timer2: timer@48040000  {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48040000  0x400>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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			ti,hwmods = "timer2";
		};

		timer3: timer@48042000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48042000 0x400>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer3";
			status = "disabled";
		};

		timer4: timer@48044000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48044000 0x400>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer4";
			status = "disabled";
		};

		timer5: timer@48046000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48046000 0x400>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer5";
			status = "disabled";
		};

		timer6: timer@48048000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48048000 0x400>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer6";
			status = "disabled";
		};

		timer7: timer@4804a000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4804a000 0x400>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			ti,timer-pwm;
			ti,hwmods = "timer7";
			status = "disabled";
		};

		timer8: timer@481c1000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x481c1000 0x400>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer8";
			status = "disabled";
		};

		timer9: timer@4833d000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833d000 0x400>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer9";
			status = "disabled";
		};

		timer10: timer@4833f000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x4833f000 0x400>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer10";
			status = "disabled";
		};

		timer11: timer@48341000 {
			compatible = "ti,am4372-timer","ti,am335x-timer";
			reg = <0x48341000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "timer11";
			status = "disabled";
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		};

		counter32k: counter@44e86000 {
			compatible = "ti,am4372-counter32k","ti,omap-counter32k";
			reg = <0x44e86000 0x40>;
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			ti,hwmods = "counter_32k";
		};

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		rtc: rtc@44e3e000 {
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			compatible = "ti,am4372-rtc","ti,da830-rtc";
			reg = <0x44e3e000 0x1000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "rtc";
			status = "disabled";
		};

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		wdt: wdt@44e35000 {
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			compatible = "ti,am4372-wdt","ti,omap3-wdt";
			reg = <0x44e35000 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "wd_timer2";
		};

		gpio0: gpio@44e07000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x44e07000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio1";
			status = "disabled";
		};

		gpio1: gpio@4804c000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x4804c000 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio2";
			status = "disabled";
		};

		gpio2: gpio@481ac000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ac000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio3";
			status = "disabled";
		};

		gpio3: gpio@481ae000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x481ae000 0x1000>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio4";
			status = "disabled";
		};

		gpio4: gpio@48320000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48320000 0x1000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio5";
			status = "disabled";
		};

		gpio5: gpio@48322000 {
			compatible = "ti,am4372-gpio","ti,omap4-gpio";
			reg = <0x48322000 0x1000>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,hwmods = "gpio6";
			status = "disabled";
		};

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		hwspinlock: spinlock@480ca000 {
			compatible = "ti,omap4-hwspinlock";
			reg = <0x480ca000 0x1000>;
			ti,hwmods = "spinlock";
			#hwlock-cells = <1>;
		};

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		i2c0: i2c@44e0b000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x44e0b000 0x1000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@4802a000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4802a000 0x1000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@4819c000 {
			compatible = "ti,am4372-i2c","ti,omap4-i2c";
			reg = <0x4819c000 0x1000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "i2c3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi0: spi@48030000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48030000 0x400>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi0";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

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		mmc1: mmc@48060000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x48060000 0x1000>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&edma 24
				&edma 25>;
			dma-names = "tx", "rx";
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		mmc2: mmc@481d8000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x481d8000 0x1000>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&edma 2
				&edma 3>;
			dma-names = "tx", "rx";
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		mmc3: mmc@47810000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x47810000 0x1000>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

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		spi1: spi@481a0000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a0000 0x400>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi1";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@481a2000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a2000 0x400>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi2";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi3: spi@481a4000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x481a4000 0x400>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi3";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi4: spi@48345000 {
			compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
			reg = <0x48345000 0x400>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "spi4";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mac: ethernet@4a100000 {
			compatible = "ti,am4372-cpsw","ti,cpsw";
			reg = <0x4a100000 0x800
			       0x4a101200 0x100>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
549
550
			#address-cells = <1>;
			#size-cells = <1>;
551
			ti,hwmods = "cpgmac0";
552
553
			clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
			clock-names = "fck", "cpts";
554
			status = "disabled";
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
			cpdma_channels = <8>;
			ale_entries = <1024>;
			bd_ram_size = <0x2000>;
			no_bd_ram = <0>;
			rx_descs = <64>;
			mac_control = <0x20>;
			slaves = <2>;
			active_slave = <0>;
			cpts_clock_mult = <0x80000000>;
			cpts_clock_shift = <29>;
			ranges;

			davinci_mdio: mdio@4a101000 {
				compatible = "ti,am4372-mdio","ti,davinci_mdio";
				reg = <0x4a101000 0x100>;
				#address-cells = <1>;
				#size-cells = <0>;
				ti,hwmods = "davinci_mdio";
				bus_freq = <1000000>;
				status = "disabled";
			};

			cpsw_emac0: slave@4a100200 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};

			cpsw_emac1: slave@4a100300 {
				/* Filled in by U-Boot */
				mac-address = [ 00 00 00 00 00 00 ];
			};
586
587
588
589
590
591

			phy_sel: cpsw-phy-sel@44e10650 {
				compatible = "ti,am43xx-cpsw-phy-sel";
				reg= <0x44e10650 0x4>;
				reg-names = "gmii-sel";
			};
592
593
594
595
596
		};

		epwmss0: epwmss@48300000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48300000 0x10>;
597
598
599
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
600
601
			ti,hwmods = "epwmss0";
			status = "disabled";
602
603
604

			ecap0: ecap@48300100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
605
				#pwm-cells = <3>;
606
607
608
609
610
611
612
				reg = <0x48300100 0x80>;
				ti,hwmods = "ecap0";
				status = "disabled";
			};

			ehrpwm0: ehrpwm@48300200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
613
				#pwm-cells = <3>;
614
615
616
617
				reg = <0x48300200 0x80>;
				ti,hwmods = "ehrpwm0";
				status = "disabled";
			};
618
619
620
621
622
		};

		epwmss1: epwmss@48302000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48302000 0x10>;
623
624
625
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
626
627
			ti,hwmods = "epwmss1";
			status = "disabled";
628
629
630

			ecap1: ecap@48302100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
631
				#pwm-cells = <3>;
632
633
634
635
636
637
638
				reg = <0x48302100 0x80>;
				ti,hwmods = "ecap1";
				status = "disabled";
			};

			ehrpwm1: ehrpwm@48302200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
639
				#pwm-cells = <3>;
640
641
642
643
				reg = <0x48302200 0x80>;
				ti,hwmods = "ehrpwm1";
				status = "disabled";
			};
644
645
646
647
648
		};

		epwmss2: epwmss@48304000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48304000 0x10>;
649
650
651
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
652
653
			ti,hwmods = "epwmss2";
			status = "disabled";
654
655
656

			ecap2: ecap@48304100 {
				compatible = "ti,am4372-ecap","ti,am33xx-ecap";
657
				#pwm-cells = <3>;
658
659
660
661
662
663
664
				reg = <0x48304100 0x80>;
				ti,hwmods = "ecap2";
				status = "disabled";
			};

			ehrpwm2: ehrpwm@48304200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
665
				#pwm-cells = <3>;
666
667
668
669
				reg = <0x48304200 0x80>;
				ti,hwmods = "ehrpwm2";
				status = "disabled";
			};
670
671
672
673
674
		};

		epwmss3: epwmss@48306000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48306000 0x10>;
675
676
677
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
678
679
			ti,hwmods = "epwmss3";
			status = "disabled";
680
681
682

			ehrpwm3: ehrpwm@48306200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
683
				#pwm-cells = <3>;
684
685
686
687
				reg = <0x48306200 0x80>;
				ti,hwmods = "ehrpwm3";
				status = "disabled";
			};
688
689
690
691
692
		};

		epwmss4: epwmss@48308000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x48308000 0x10>;
693
694
695
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
696
697
			ti,hwmods = "epwmss4";
			status = "disabled";
698
699
700

			ehrpwm4: ehrpwm@48308200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
701
				#pwm-cells = <3>;
702
703
704
705
				reg = <0x48308200 0x80>;
				ti,hwmods = "ehrpwm4";
				status = "disabled";
			};
706
707
708
709
710
		};

		epwmss5: epwmss@4830a000 {
			compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
			reg = <0x4830a000 0x10>;
711
712
713
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
714
715
			ti,hwmods = "epwmss5";
			status = "disabled";
716
717
718

			ehrpwm5: ehrpwm@4830a200 {
				compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
719
				#pwm-cells = <3>;
720
721
722
723
724
725
				reg = <0x4830a200 0x80>;
				ti,hwmods = "ehrpwm5";
				status = "disabled";
			};
		};

726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
		tscadc: tscadc@44e0d000 {
			compatible = "ti,am3359-tscadc";
			reg = <0x44e0d000 0x1000>;
			ti,hwmods = "adc_tsc";
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&adc_tsc_fck>;
			clock-names = "fck";
			status = "disabled";

			tsc {
				compatible = "ti,am3359-tsc";
			};

			adc {
				#io-channel-cells = <1>;
				compatible = "ti,am3359-adc";
			};

		};

746
747
748
749
750
751
752
		sham: sham@53100000 {
			compatible = "ti,omap5-sham";
			ti,hwmods = "sham";
			reg = <0x53100000 0x300>;
			dmas = <&edma 36>;
			dma-names = "rx";
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
753
		};
754
755
756
757
758
759

		aes: aes@53501000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes";
			reg = <0x53501000 0xa0>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
760
761
762
			dmas = <&edma 6
				&edma 5>;
			dma-names = "tx", "rx";
763
		};
764
765
766
767
768
769

		des: des@53701000 {
			compatible = "ti,omap4-des";
			ti,hwmods = "des";
			reg = <0x53701000 0xa0>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
770
771
772
			dmas = <&edma 34
				&edma 33>;
			dma-names = "tx", "rx";
773
		};
774

775
776
777
778
779
780
781
		mcasp0: mcasp@48038000 {
			compatible = "ti,am33xx-mcasp-audio";
			ti,hwmods = "mcasp0";
			reg = <0x48038000 0x2000>,
			      <0x46000000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <80>, <81>;
782
			interrupt-names = "tx", "rx";
783
784
785
786
787
788
789
790
791
792
793
794
795
			status = "disabled";
			dmas = <&edma 8>,
			       <&edma 9>;
			dma-names = "tx", "rx";
		};

		mcasp1: mcasp@4803C000 {
			compatible = "ti,am33xx-mcasp-audio";
			ti,hwmods = "mcasp1";
			reg = <0x4803C000 0x2000>,
			      <0x46400000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <82>, <83>;
796
			interrupt-names = "tx", "rx";
797
798
799
800
801
			status = "disabled";
			dmas = <&edma 10>,
			       <&edma 11>;
			dma-names = "tx", "rx";
		};
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825

		elm: elm@48080000 {
			compatible = "ti,am3352-elm";
			reg = <0x48080000 0x2000>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			ti,hwmods = "elm";
			clocks = <&l4ls_gclk>;
			clock-names = "fck";
			status = "disabled";
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,am3352-gpmc";
			ti,hwmods = "gpmc";
			clocks = <&l3s_gclk>;
			clock-names = "fck";
			reg = <0x50000000 0x2000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			gpmc,num-cs = <7>;
			gpmc,num-waitpins = <2>;
			#address-cells = <2>;
			#size-cells = <1>;
			status = "disabled";
		};
826
827
828
829
830
831
832
833
834
835
836
837
838
839

		am43xx_control_usb2phy1: control-phy@44e10620 {
			compatible = "ti,control-phy-usb2-am437";
			reg = <0x44e10620 0x4>;
			reg-names = "power";
		};

		am43xx_control_usb2phy2: control-phy@0x44e10628 {
			compatible = "ti,control-phy-usb2-am437";
			reg = <0x44e10628 0x4>;
			reg-names = "power";
		};

		ocp2scp0: ocp2scp@483a8000 {
840
			compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "ocp2scp0";

			usb2_phy1: phy@483a8000 {
				compatible = "ti,am437x-usb2";
				reg = <0x483a8000 0x8000>;
				ctrl-module = <&am43xx_control_usb2phy1>;
				clocks = <&usb_phy0_always_on_clk32k>,
					 <&usb_otg_ss0_refclk960m>;
				clock-names = "wkupclk", "refclk";
				#phy-cells = <0>;
				status = "disabled";
			};
		};

		ocp2scp1: ocp2scp@483e8000 {
859
			compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "ocp2scp1";

			usb2_phy2: phy@483e8000 {
				compatible = "ti,am437x-usb2";
				reg = <0x483e8000 0x8000>;
				ctrl-module = <&am43xx_control_usb2phy2>;
				clocks = <&usb_phy1_always_on_clk32k>,
					 <&usb_otg_ss1_refclk960m>;
				clock-names = "wkupclk", "refclk";
				#phy-cells = <0>;
				status = "disabled";
			};
		};

		dwc3_1: omap_dwc3@48380000 {
			compatible = "ti,am437x-dwc3";
			ti,hwmods = "usb_otg_ss0";
			reg = <0x48380000 0x10000>;
			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <1>;
			ranges;

			usb1: usb@48390000 {
				compatible = "synopsys,dwc3";
889
				reg = <0x48390000 0x10000>;
890
891
892
893
894
895
				interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "peripheral",
						  "host",
						  "otg";
896
897
898
899
900
				phys = <&usb2_phy1>;
				phy-names = "usb2-phy";
				maximum-speed = "high-speed";
				dr_mode = "otg";
				status = "disabled";
901
902
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
			};
		};

		dwc3_2: omap_dwc3@483c0000 {
			compatible = "ti,am437x-dwc3";
			ti,hwmods = "usb_otg_ss1";
			reg = <0x483c0000 0x10000>;
			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <1>;
			ranges;

			usb2: usb@483d0000 {
				compatible = "synopsys,dwc3";
918
				reg = <0x483d0000 0x10000>;
919
920
921
922
923
924
				interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "peripheral",
						  "host",
						  "otg";
925
926
927
928
929
				phys = <&usb2_phy2>;
				phy-names = "usb2-phy";
				maximum-speed = "high-speed";
				dr_mode = "otg";
				status = "disabled";
930
931
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
932
933
			};
		};
934
935
936
937
938
939
940
941
942
943
944

		qspi: qspi@47900000 {
			compatible = "ti,am4372-qspi";
			reg = <0x47900000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "qspi";
			interrupts = <0 138 0x4>;
			num-cs = <4>;
			status = "disabled";
		};
945
946

		hdq: hdq@48347000 {
947
			compatible = "ti,am4372-hdq";
948
949
950
951
952
953
954
			reg = <0x48347000 0x1000>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&func_12m_clk>;
			clock-names = "fck";
			ti,hwmods = "hdq1w";
			status = "disabled";
		};
955
956
957
958
959
960
961
962
963
964
965
966

		dss: dss@4832a000 {
			compatible = "ti,omap3-dss";
			reg = <0x4832a000 0x200>;
			status = "disabled";
			ti,hwmods = "dss_core";
			clocks = <&disp_clk>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

967
			dispc: dispc@4832a400 {
968
969
970
971
972
973
974
975
976
977
978
979
980
981
				compatible = "ti,omap3-dispc";
				reg = <0x4832a400 0x400>;
				interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
				ti,hwmods = "dss_dispc";
				clocks = <&disp_clk>;
				clock-names = "fck";
			};

			rfbi: rfbi@4832a800 {
				compatible = "ti,omap3-rfbi";
				reg = <0x4832a800 0x100>;
				ti,hwmods = "dss_rfbi";
				clocks = <&disp_clk>;
				clock-names = "fck";
982
				status = "disabled";
983
984
			};
		};
985
986
987
988
989

		ocmcram: ocmcram@40300000 {
			compatible = "mmio-sram";
			reg = <0x40300000 0x40000>; /* 256k */
		};
990
991
992
993
994
995
996

		dcan0: can@481cc000 {
			compatible = "ti,am4372-d_can", "ti,am3352-d_can";
			ti,hwmods = "d_can0";
			clocks = <&dcan0_fck>;
			clock-names = "fck";
			reg = <0x481cc000 0x2000>;
997
			syscon-raminit = <&scm_conf 0x644 0>;
998
999
1000
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};
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