Commit 11777ee8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'i2c/for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull i2c updates from Wolfram Sang:
 "i2c core:

   - huge improvements and refactorizations of the Linux I2C
     documentation (lots of thanks to Luca for doing it and Jean for the
     careful review)

   - subsystem wide API conversion to i2c_new_client_device()

   - remove obsolete parport-light driver

   - smaller core updates (removal of 'extern', enabling more compile
     testing, use more helper macros)

   - and quite a bunch of driver updates (new IDs, simplifications,
     better PM, support of atomic transfers and other improvements)

  i2c-mux:

   - The main feature is the idle-state rework of the pca954x driver
     from Biwen Li

  at24 driver:

   - minor maintenance: update the license tag, sort headers

   - move support for the write-protect pin into nvmem core

   - add a reference to the new wp-gpios property in nvmem to at25
     bindings

   - add support for regulator and pm_runtime control"

* 'i2c/for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (91 commits)
  i2c: cros-ec-tunnel: Fix ACPI identifier
  i2c: cros-ec-tunnel: Fix slave device enumeration
  i2c: stm32f7: add PM_SLEEP suspend/resume support
  i2c: cadence: Fix wording in i2c-cadence driver
  i2c: cadence: Fix power management order of operations
  i2c: cadence: Fix error printing in case of defer
  i2c: cadence: Handle transfer_size rollover
  i2c: i801: Add support for Intel Comet Lake PCH-V
  docs: i2c: writing-clients: properly name the stop condition
  docs: i2c: i2c-protocol: use same wording as smbus-protocol
  docs: i2c: rename sections so the overall picture is clearer
  docs: i2c: old-module-parameters: use monospace instead of ""
  docs: i2c: old-module-parameters: clarify this is for obsolete kernels
  docs: i2c: old-module-parameters: fix internal hyperlink
  docs: i2c: instantiating-devices: use monospace for sysfs attributes
  docs: i2c: instantiating-devices: rearrange static instatiation
  docs: i2c: instantiating-devices: fix internal hyperlink
  docs: i2c: smbus-protocol: improve I2C Block transactions description
  docs: i2c: smbus-protocol: fix punctuation
  docs: i2c: smbus-protocol: fix typo
  ...
parents ed39ba0e b49f8e0e
......@@ -145,10 +145,7 @@ properties:
over reads to the next slave address. Please consult the manual of
your device.
wp-gpios:
description:
GPIO to which the write-protect pin of the chip is connected.
maxItems: 1
wp-gpios: true
address-width:
allOf:
......@@ -167,6 +164,10 @@ properties:
minimum: 1
maximum: 8
vcc-supply:
description:
phandle of the regulator that provides the supply voltage.
required:
- compatible
- reg
......
......@@ -20,6 +20,7 @@ Optional properties:
- spi-cpha : SPI shifted clock phase, as per spi-bus bindings.
- spi-cpol : SPI inverse clock polarity, as per spi-bus bindings.
- read-only : this parameter-less property disables writes to the eeprom
- wp-gpios : GPIO to which the write-protect pin of the chip is connected
Obsolete legacy properties can be used in place of "size", "pagesize",
"address-width", and "read-only":
......@@ -36,6 +37,7 @@ Example:
spi-max-frequency = <5000000>;
spi-cpha;
spi-cpol;
wp-gpios = <&gpio1 3 0>;
pagesize = <64>;
size = <32768>;
......
I2C for Atmel platforms
Required properties :
- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
"atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
"atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c", "atmel,sama5d2-i2c" or
"microchip,sam9x60-i2c"
- compatible : Must be one of:
"atmel,at91rm9200-i2c",
"atmel,at91sam9261-i2c",
"atmel,at91sam9260-i2c",
"atmel,at91sam9g20-i2c",
"atmel,at91sam9g10-i2c",
"atmel,at91sam9x5-i2c",
"atmel,sama5d4-i2c",
"atmel,sama5d2-i2c",
"microchip,sam9x60-i2c".
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
......
* Ingenic JZ4780 I2C Bus controller
Required properties:
- compatible: should be "ingenic,jz4780-i2c"
- compatible: should be one of the following:
- "ingenic,jz4780-i2c" for the JZ4780
- "ingenic,x1000-i2c" for the X1000
- reg: Should contain the address & size of the I2C controller registers.
- interrupts: Should specify the interrupt provided by parent.
- clocks: Should contain a single clock specifier for the JZ4780 I2C clock.
......
......@@ -25,6 +25,8 @@ Required Properties:
Optional Properties:
- reset-gpios: Reference to the GPIO connected to the reset input.
- idle-state: if present, overrides i2c-mux-idle-disconnect,
Please refer to Documentation/devicetree/bindings/mux/mux-controller.txt
- i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all
children in idle state. This is necessary for example, if there are several
multiplexers on the bus and the devices behind them use same I2C addresses.
......
......@@ -17,7 +17,8 @@ Required properties:
"renesas,i2c-r8a7793" if the device is a part of a R8A7793 SoC.
"renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
"renesas,i2c-r8a7796" if the device is a part of a R8A77960 SoC.
"renesas,i2c-r8a77961" if the device is a part of a R8A77961 SoC.
"renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC.
"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
"renesas,i2c-r8a77980" if the device is a part of a R8A77980 SoC.
......
......@@ -17,6 +17,7 @@ Required properties:
- "renesas,iic-r8a7794" (R-Car E2)
- "renesas,iic-r8a7795" (R-Car H3)
- "renesas,iic-r8a7796" (R-Car M3-W)
- "renesas,iic-r8a77961" (R-Car M3-W+)
- "renesas,iic-r8a77965" (R-Car M3-N)
- "renesas,iic-r8a77990" (R-Car E3)
- "renesas,iic-sh73a0" (SH-Mobile AG5)
......
......@@ -34,6 +34,14 @@ properties:
description:
Mark the provider as read only.
wp-gpios:
description:
GPIO to which the write-protect pin of the chip is connected.
The write-protect GPIO is asserted, when it's driven high
(logical '1') to block the write operation. It's deasserted,
when it's driven low (logical '0') to allow writing.
maxItems: 1
patternProperties:
"^.*@[0-9a-f]+$":
type: object
......@@ -63,9 +71,12 @@ patternProperties:
examples:
- |
#include <dt-bindings/gpio/gpio.h>
qfprom: eeprom@700000 {
#address-cells = <1>;
#size-cells = <1>;
wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
/* ... */
......
===============================
Kernel driver i2c-parport-light
===============================
Author: Jean Delvare <jdelvare@suse.de>
This driver is a light version of i2c-parport. It doesn't depend
on the parport driver, and uses direct I/O access instead. This might be
preferred on embedded systems where wasting memory for the clean but heavy
parport handling is not an option. The drawback is a reduced portability
and the impossibility to daisy-chain other parallel port devices.
Please see i2c-parport for documentation.
Module parameters:
* type: type of adapter (see i2c-parport or modinfo)
* base: base I/O address
Default is 0x378 which is fairly common for parallel ports, at least on PC.
* irq: optional IRQ
This must be passed if you want SMBus alert support, assuming your adapter
actually supports this.
......@@ -20,7 +20,6 @@ I2C Bus Drivers
i2c-nforce2
i2c-nvidia-gpu
i2c-ocores
i2c-parport-light
i2c-parport
i2c-pca-isa
i2c-piix4
......
====================
I2C Device Interface
====================
============================================
Implementing I2C device drivers in userspace
============================================
Usually, i2c devices are controlled by a kernel driver. But it is also
Usually, I2C devices are controlled by a kernel driver. But it is also
possible to access all devices on an adapter from userspace, through
the /dev interface. You need to load module i2c-dev for this.
Each registered i2c adapter gets a number, counting from 0. You can
Each registered I2C adapter gets a number, counting from 0. You can
examine /sys/class/i2c-dev/ to see what number corresponds to which adapter.
Alternatively, you can run "i2cdetect -l" to obtain a formatted list of all
i2c adapters present on your system at a given time. i2cdetect is part of
I2C adapters present on your system at a given time. i2cdetect is part of
the i2c-tools package.
I2C device files are character device files with major device number 89
and a minor device number corresponding to the number assigned as
explained above. They should be called "i2c-%d" (i2c-0, i2c-1, ...,
i2c-10, ...). All 256 minor device numbers are reserved for i2c.
i2c-10, ...). All 256 minor device numbers are reserved for I2C.
C example
=========
So let's say you want to access an i2c adapter from a C program.
So let's say you want to access an I2C adapter from a C program.
First, you need to include these two headers::
#include <linux/i2c-dev.h>
......@@ -66,7 +66,7 @@ the device supports them. Both are illustrated below::
/* Using SMBus commands */
res = i2c_smbus_read_word_data(file, reg);
if (res < 0) {
/* ERROR HANDLING: i2c transaction failed */
/* ERROR HANDLING: I2C transaction failed */
} else {
/* res contains the read word */
}
......@@ -79,12 +79,12 @@ the device supports them. Both are illustrated below::
buf[1] = 0x43;
buf[2] = 0x65;
if (write(file, buf, 3) != 3) {
/* ERROR HANDLING: i2c transaction failed */
/* ERROR HANDLING: I2C transaction failed */
}
/* Using I2C Read, equivalent of i2c_smbus_read_byte(file) */
if (read(file, buf, 1) != 1) {
/* ERROR HANDLING: i2c transaction failed */
/* ERROR HANDLING: I2C transaction failed */
} else {
/* buf[0] contains the read byte */
}
......@@ -144,7 +144,7 @@ The following IOCTLs are defined:
If possible, use the provided ``i2c_smbus_*`` methods described below instead
of issuing direct ioctls.
You can do plain i2c transactions by using read(2) and write(2) calls.
You can do plain I2C transactions by using read(2) and write(2) calls.
You do not need to pass the address byte; instead, set it through
ioctl I2C_SLAVE before you try to access the device.
......
......@@ -2,7 +2,7 @@
Linux I2C and DMA
=================
Given that i2c is a low-speed bus, over which the majority of messages
Given that I2C is a low-speed bus, over which the majority of messages
transferred are small, it is not considered a prime user of DMA access. At this
time of writing, only 10% of I2C bus master drivers have DMA support
implemented. And the vast majority of transactions are so small that setting up
......
============
I2C Protocol
============
================
The I2C Protocol
================
This document describes the i2c protocol. Or will, when it is finished :-)
This document describes the I2C protocol. Or will, when it is finished :-)
Key to symbols
==============
=============== =============================================================
S (1 bit) : Start bit
P (1 bit) : Stop bit
Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0.
A, NA (1 bit) : Accept and reverse accept bit.
Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
S Start condition
P Stop condition
Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit
Addr (7 bits) I2C 7 bit address. Note that this can be expanded as usual to
get a 10 bit I2C address.
Comm (8 bits): Command byte, a data byte which often selects a register on
Comm (8 bits) Command byte, a data byte which often selects a register on
the device.
Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh
Data (8 bits) A plain data byte. Sometimes, I write DataLow, DataHigh
for 16 bit data.
Count (8 bits): A data byte containing the length of a block operation.
Count (8 bits) A data byte containing the length of a block operation.
[..]: Data sent by I2C device, as opposed to data sent by the
[..] Data sent by I2C device, as opposed to data sent by the
host adapter.
=============== =============================================================
......@@ -28,7 +28,7 @@ Count (8 bits): A data byte containing the length of a block operation.
Simple send transaction
=======================
This corresponds to i2c_master_send::
Implemented by i2c_master_send()::
S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P
......@@ -36,7 +36,7 @@ This corresponds to i2c_master_send::
Simple receive transaction
==========================
This corresponds to i2c_master_recv::
Implemented by i2c_master_recv()::
S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
......@@ -44,11 +44,11 @@ This corresponds to i2c_master_recv::
Combined transactions
=====================
This corresponds to i2c_transfer
Implemented by i2c_transfer().
They are just like the above transactions, but instead of a stop bit P
a start bit S is sent and the transaction continues. An example of
a byte read, followed by a byte write::
They are just like the above transactions, but instead of a stop
condition P a start condition S is sent and the transaction continues.
An example of a byte read, followed by a byte write::
S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P
......@@ -57,7 +57,7 @@ Modified transactions
=====================
The following modifications to the I2C protocol can also be generated by
setting these flags for i2c messages. With the exception of I2C_M_NOSTART, they
setting these flags for I2C messages. With the exception of I2C_M_NOSTART, they
are usually only needed to work around device issues:
I2C_M_IGNORE_NAK:
......@@ -77,8 +77,9 @@ I2C_M_NOSTART:
S Addr Rd [A] [Data] NA Data [A] P
If you set the I2C_M_NOSTART variable for the first partial message,
we do not generate Addr, but we do generate the startbit S. This will
probably confuse all other clients on your bus, so don't try this.
we do not generate Addr, but we do generate the start condition S.
This will probably confuse all other clients on your bus, so don't
try this.
This is often used to gather transmits from multiple data buffers in
system memory into something that appears as a single transfer to the
......
============
I2C topology
============
================================
I2C muxes and complex topologies
================================
There are a couple of reasons for building more complex i2c topologies
than a straight-forward i2c bus with one adapter and one or more devices.
There are a couple of reasons for building more complex I2C topologies
than a straight-forward I2C bus with one adapter and one or more devices.
1. A mux may be needed on the bus to prevent address collisions.
......@@ -11,20 +11,20 @@ than a straight-forward i2c bus with one adapter and one or more devices.
may be needed to determine if it is ok to access the bus.
3. A device (particularly RF tuners) may want to avoid the digital noise
from the i2c bus, at least most of the time, and sits behind a gate
from the I2C bus, at least most of the time, and sits behind a gate
that has to be operated before the device can be accessed.
Etc
===
These constructs are represented as i2c adapter trees by Linux, where
These constructs are represented as I2C adapter trees by Linux, where
each adapter has a parent adapter (except the root adapter) and zero or
more child adapters. The root adapter is the actual adapter that issues
i2c transfers, and all adapters with a parent are part of an "i2c-mux"
I2C transfers, and all adapters with a parent are part of an "i2c-mux"
object (quoted, since it can also be an arbitrator or a gate).
Depending of the particular mux driver, something happens when there is
an i2c transfer on one of its child adapters. The mux driver can
an I2C transfer on one of its child adapters. The mux driver can
obviously operate a mux, but it can also do arbitration with an external
bus master or open a gate. The mux driver has two operations for this,
select and deselect. select is called before the transfer and (the
......@@ -34,7 +34,7 @@ optional) deselect is called after the transfer.
Locking
=======
There are two variants of locking available to i2c muxes, they can be
There are two variants of locking available to I2C muxes, they can be
mux-locked or parent-locked muxes. As is evident from below, it can be
useful to know if a mux is mux-locked or if it is parent-locked. The
following list was correct at the time of writing:
......@@ -45,7 +45,7 @@ In drivers/i2c/muxes/:
i2c-arb-gpio-challenge Parent-locked
i2c-mux-gpio Normally parent-locked, mux-locked iff
all involved gpio pins are controlled by the
same i2c root adapter that they mux.
same I2C root adapter that they mux.
i2c-mux-gpmux Normally parent-locked, mux-locked iff
specified in device-tree.
i2c-mux-ltc4306 Mux-locked
......@@ -54,7 +54,7 @@ i2c-mux-pca9541 Parent-locked
i2c-mux-pca954x Parent-locked
i2c-mux-pinctrl Normally parent-locked, mux-locked iff
all involved pinctrl devices are controlled
by the same i2c root adapter that they mux.
by the same I2C root adapter that they mux.
i2c-mux-reg Parent-locked
====================== =============================================
......@@ -83,9 +83,9 @@ Mux-locked muxes
Mux-locked muxes does not lock the entire parent adapter during the
full select-transfer-deselect transaction, only the muxes on the parent
adapter are locked. Mux-locked muxes are mostly interesting if the
select and/or deselect operations must use i2c transfers to complete
select and/or deselect operations must use I2C transfers to complete
their tasks. Since the parent adapter is not fully locked during the
full transaction, unrelated i2c transfers may interleave the different
full transaction, unrelated I2C transfers may interleave the different
stages of the transaction. This has the benefit that the mux driver
may be easier and cleaner to implement, but it has some caveats.
......@@ -109,14 +109,14 @@ ML2. It is not safe to build arbitrary topologies with two (or more)
ML3. A mux-locked mux cannot be used by a driver for auto-closing
gates/muxes, i.e. something that closes automatically after a given
number (one, in most cases) of i2c transfers. Unrelated i2c transfers
number (one, in most cases) of I2C transfers. Unrelated I2C transfers
may creep in and close prematurely.
ML4. If any non-i2c operation in the mux driver changes the i2c mux state,
ML4. If any non-I2C operation in the mux driver changes the I2C mux state,
the driver has to lock the root adapter during that operation.
Otherwise garbage may appear on the bus as seen from devices
behind the mux, when an unrelated i2c transfer is in flight during
the non-i2c mux-changing operation.
behind the mux, when an unrelated I2C transfer is in flight during
the non-I2C mux-changing operation.
==== =====================================================================
......@@ -137,14 +137,14 @@ Mux-locked Example
When there is an access to D1, this happens:
1. Someone issues an i2c-transfer to D1.
1. Someone issues an I2C transfer to D1.
2. M1 locks muxes on its parent (the root adapter in this case).
3. M1 calls ->select to ready the mux.
4. M1 (presumably) does some i2c-transfers as part of its select.
These transfers are normal i2c-transfers that locks the parent
4. M1 (presumably) does some I2C transfers as part of its select.
These transfers are normal I2C transfers that locks the parent
adapter.
5. M1 feeds the i2c-transfer from step 1 to its parent adapter as a
normal i2c-transfer that locks the parent adapter.
5. M1 feeds the I2C transfer from step 1 to its parent adapter as a
normal I2C transfer that locks the parent adapter.
6. M1 calls ->deselect, if it has one.
7. Same rules as in step 4, but for ->deselect.
8. M1 unlocks muxes on its parent.
......@@ -159,8 +159,8 @@ Parent-locked muxes
Parent-locked muxes lock the parent adapter during the full select-
transfer-deselect transaction. The implication is that the mux driver
has to ensure that any and all i2c transfers through that parent
adapter during the transaction are unlocked i2c transfers (using e.g.
has to ensure that any and all I2C transfers through that parent
adapter during the transaction are unlocked I2C transfers (using e.g.
__i2c_transfer), or a deadlock will follow. There are a couple of
caveats.
......@@ -169,12 +169,12 @@ PL1. If you build a topology with a parent-locked mux being the child
of another mux, this might break a possible assumption from the
child mux that the root adapter is unused between its select op
and the actual transfer (e.g. if the child mux is auto-closing
and the parent mux issus i2c-transfers as part of its select).
and the parent mux issues I2C transfers as part of its select).
This is especially the case if the parent mux is mux-locked, but
it may also happen if the parent mux is parent-locked.
PL2. If select/deselect calls out to other subsystems such as gpio,
pinctrl, regmap or iio, it is essential that any i2c transfers
pinctrl, regmap or iio, it is essential that any I2C transfers
caused by these subsystems are unlocked. This can be convoluted to
accomplish, maybe even impossible if an acceptably clean solution
is sought.
......@@ -197,15 +197,15 @@ Parent-locked Example
When there is an access to D1, this happens:
1. Someone issues an i2c-transfer to D1.
1. Someone issues an I2C transfer to D1.
2. M1 locks muxes on its parent (the root adapter in this case).
3. M1 locks its parent adapter.
4. M1 calls ->select to ready the mux.
5. If M1 does any i2c-transfers (on this root adapter) as part of
its select, those transfers must be unlocked i2c-transfers so
5. If M1 does any I2C transfers (on this root adapter) as part of
its select, those transfers must be unlocked I2C transfers so
that they do not deadlock the root adapter.
6. M1 feeds the i2c-transfer from step 1 to the root adapter as an
unlocked i2c-transfer, so that it does not deadlock the parent
6. M1 feeds the I2C transfer from step 1 to the root adapter as an
unlocked I2C transfer, so that it does not deadlock the parent
adapter.
7. M1 calls ->deselect, if it has one.
8. Same rules as in step 5, but for ->deselect.
......@@ -240,7 +240,7 @@ and specifically when M2 requests its parent to lock, M1 passes
the buck to the root adapter).
This topology is bad if M2 is an auto-closing mux and M1->select
issues any unlocked i2c transfers on the root adapter that may leak
issues any unlocked I2C transfers on the root adapter that may leak
through and be seen by the M2 adapter, thus closing M2 prematurely.
......@@ -286,14 +286,14 @@ point.
This kind of topology is generally not suitable and should probably
be avoided. The reason is that M2 probably assumes that there will
be no i2c transfers during its calls to ->select and ->deselect, and
be no I2C transfers during its calls to ->select and ->deselect, and
if there are, any such transfers might appear on the slave side of M2
as partial i2c transfers, i.e. garbage or worse. This might cause
as partial I2C transfers, i.e. garbage or worse. This might cause
device lockups and/or other problems.
The topology is especially troublesome if M2 is an auto-closing
mux. In that case, any interleaved accesses to D4 might close M2
prematurely, as might any i2c-transfers part of M1->select.
prematurely, as might any I2C transfers part of M1->select.
But if M2 is not making the above stated assumption, and if M2 is not
auto-closing, the topology is fine.
......
This diff is collapsed.
......@@ -4,30 +4,66 @@
I2C/SMBus Subsystem
===================
Introduction
============
.. toctree::
:maxdepth: 1
summary
i2c-protocol
smbus-protocol
instantiating-devices
busses/index
i2c-topology
muxes/i2c-mux-gpio
Writing device drivers
======================
.. toctree::
:maxdepth: 1
writing-clients
dev-interface
dma-considerations
fault-codes
functionality
Debugging
=========
.. toctree::
:maxdepth: 1
gpio-fault-injection
i2c-protocol
i2c-stub
i2c-topology
instantiating-devices
old-module-parameters
slave-eeprom-backend
Slave I2C
=========
.. toctree::
:maxdepth: 1
slave-interface
smbus-protocol
summary
slave-eeprom-backend
Advanced topics
===============
.. toctree::
:maxdepth: 1
ten-bit-addresses
upgrading-clients
writing-clients
muxes/i2c-mux-gpio
Legacy documentation
====================
busses/index
.. toctree::
:maxdepth: 1
upgrading-clients
old-module-parameters
.. only:: subproject and html
......
......@@ -9,54 +9,27 @@ reason, the kernel code must instantiate I2C devices explicitly. There are
several ways to achieve this, depending on the context and requirements.
Method 1a: Declare the I2C devices by bus number
------------------------------------------------
Method 1: Declare the I2C devices statically
--------------------------------------------
This method is appropriate when the I2C bus is a system bus as is the case
for many embedded systems. On such systems, each I2C bus has a number
which is known in advance. It is thus possible to pre-declare the I2C
devices which live on this bus. This is done with an array of struct
i2c_board_info which is registered by calling i2c_register_board_info().
for many embedded systems. On such systems, each I2C bus has a number which
is known in advance. It is thus possible to pre-declare the I2C devices
which live on this bus.
Example (from omap2 h4)::
This information is provided to the kernel in a different way on different
architectures: device tree, ACPI or board files.
static struct i2c_board_info h4_i2c_board_info[] __initdata = {
{
I2C_BOARD_INFO("isp1301_omap", 0x2d),
.irq = OMAP_GPIO_IRQ(125),
},