Commit 469030d4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC platform updates from Olof Johansson:
 "Most of these are smaller fixes that have accrued, and some continued
  cleanup of OMAP platforms towards shared frameworks.

  One new SoC from Atmel/Microchip: sam9x60"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (35 commits)
  ARM: OMAP2+: Fix undefined reference to omap_secure_init
  ARM: s3c64xx: Drop unneeded select of TIMER_OF
  ARM: exynos: Drop unneeded select of MIGHT_HAVE_CACHE_L2X0
  ARM: s3c24xx: Switch to atomic pwm API in rx1950
  ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers
  ARM: OMAP2+: Use ARM SMC Calling Convention when OP-TEE is available
  ARM: OMAP2+: Introduce check for OP-TEE in omap_secure_init()
  ARM: OMAP2+: Add omap_secure_init callback hook for secure initialization
  ARM: at91: Documentation: add sam9x60 product and datasheet
  ARM: at91: pm: use of_device_id array to find the proper shdwc node
  ARM: at91: pm: use SAM9X60 PMC's compatible
  ARM: imx: only select ARM_ERRATA_814220 for ARMv7-A
  ARM: zynq: use physical cpuid in zynq_slcr_cpu_stop/start
  ARM: tegra: Use clk_m CPU on Tegra124 LP1 resume
  ARM: tegra: Modify reshift divider during LP1
  ARM: tegra: Enable PLLP bypass during Tegra124 LP1
  ARM: samsung: Rename Samsung and Exynos to lowercase
  ARM: exynos: Correct the help text for platform Kconfig option
  ARM: bcm: Select ARM_AMBA for ARCH_BRCMSTB
  ARM: brcmstb: Add debug UART entry for 7216
  ...
parents b85080c1 d8430df1
......@@ -92,6 +92,12 @@ the Microchip website: http://www.microchip.com.
http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001517A.pdf
- sam9x60
* Datasheet
http://ww1.microchip.com/downloads/en/DeviceDoc/SAM9X60-Data-Sheet-DS60001579A.pdf
* ARM Cortex-A5 based SoCs
- sama5d3 family
......
......@@ -147,14 +147,14 @@ choice
0x80024000 | 0xf0024000 | UART9
config DEBUG_AT91_RM9200_DBGU
bool "Kernel low-level debugging on AT91RM9200, AT91SAM9 DBGU"
bool "Kernel low-level debugging on AT91RM9200, AT91SAM9, SAM9X60 DBGU"
select DEBUG_AT91_UART
depends on SOC_AT91RM9200 || SOC_AT91SAM9
depends on SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60
help
Say Y here if you want kernel low-level debugging support
on the DBGU port of:
at91rm9200, at91sam9260, at91sam9g20, at91sam9261,
at91sam9g10, at91sam9n12, at91sam9rl64, at91sam9x5
at91sam9g10, at91sam9n12, at91sam9rl64, at91sam9x5, sam9x60
config DEBUG_AT91_SAM9263_DBGU
bool "Kernel low-level debugging on AT91SAM{9263,9G45,A5D3} DBGU"
......
......@@ -31,6 +31,7 @@
#define UARTA_7268 UARTA_7255
#define UARTA_7271 UARTA_7268
#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
#define UARTA_7216 UARTA_7278
#define UARTA_7364 REG_PHYS_ADDR(0x40b000)
#define UARTA_7366 UARTA_7364
#define UARTA_74371 REG_PHYS_ADDR(0x406b00)
......@@ -82,17 +83,18 @@ ARM_BE8( rev \rv, \rv )
/* Chip specific detection starts here */
20: checkuart(\rp, \rv, 0x33900000, 3390)
21: checkuart(\rp, \rv, 0x72500000, 7250)
22: checkuart(\rp, \rv, 0x72550000, 7255)
23: checkuart(\rp, \rv, 0x72600000, 7260)
24: checkuart(\rp, \rv, 0x72680000, 7268)
25: checkuart(\rp, \rv, 0x72710000, 7271)
26: checkuart(\rp, \rv, 0x72780000, 7278)
27: checkuart(\rp, \rv, 0x73640000, 7364)
28: checkuart(\rp, \rv, 0x73660000, 7366)
29: checkuart(\rp, \rv, 0x07437100, 74371)
30: checkuart(\rp, \rv, 0x74390000, 7439)
31: checkuart(\rp, \rv, 0x74450000, 7445)
21: checkuart(\rp, \rv, 0x72160000, 7216)
22: checkuart(\rp, \rv, 0x72500000, 7250)
23: checkuart(\rp, \rv, 0x72550000, 7255)
24: checkuart(\rp, \rv, 0x72600000, 7260)
25: checkuart(\rp, \rv, 0x72680000, 7268)
26: checkuart(\rp, \rv, 0x72710000, 7271)
27: checkuart(\rp, \rv, 0x72780000, 7278)
28: checkuart(\rp, \rv, 0x73640000, 7364)
29: checkuart(\rp, \rv, 0x73660000, 7366)
30: checkuart(\rp, \rv, 0x07437100, 74371)
31: checkuart(\rp, \rv, 0x74390000, 7439)
32: checkuart(\rp, \rv, 0x74450000, 7445)
/* No valid UART found */
90: mov \rp, #0
......
......@@ -105,11 +105,28 @@ config SOC_AT91SAM9
AT91SAM9X35
AT91SAM9XE
config SOC_SAM9X60
bool "SAM9X60"
depends on ARCH_MULTI_V5
select ATMEL_AIC5_IRQ
select ATMEL_PM if PM
select ATMEL_SDRAMC
select CPU_ARM926T
select HAVE_AT91_USB_CLK
select HAVE_AT91_GENERATED_CLK
select HAVE_AT91_SAM9X60_PLL
select MEMORY
select PINCTRL_AT91
select SOC_SAM_V4_V5
select SRAM if PM
help
Select this if you are using Microchip's SAM9X60 SoC
comment "Clocksource driver selection"
config ATMEL_CLOCKSOURCE_PIT
bool "Periodic Interval Timer (PIT) support"
depends on SOC_AT91SAM9 || SOC_SAMA5
depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
default SOC_AT91SAM9 || SOC_SAMA5
select ATMEL_PIT
help
......@@ -119,7 +136,7 @@ config ATMEL_CLOCKSOURCE_PIT
config ATMEL_CLOCKSOURCE_TCB
bool "Timer Counter Blocks (TCB) support"
default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAMA5
default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
select ATMEL_TCB_CLKSRC
help
Select this to get a high precision clocksource based on a
......@@ -154,6 +171,9 @@ config HAVE_AT91_AUDIO_PLL
config HAVE_AT91_I2S_MUX_CLK
bool
config HAVE_AT91_SAM9X60_PLL
bool
config SOC_SAM_V4_V5
bool
......
......@@ -6,6 +6,7 @@
# CPU-specific support
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
obj-$(CONFIG_SOC_SAMA5) += sama5.o
obj-$(CONFIG_SOC_SAMV7) += samv7.o
......
......@@ -31,21 +31,3 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9")
.init_machine = at91sam9_init,
.dt_compat = at91_dt_board_compat,
MACHINE_END
static void __init sam9x60_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
sam9x60_pm_init();
}
static const char *const sam9x60_dt_board_compat[] __initconst = {
"microchip,sam9x60",
NULL
};
DT_MACHINE_START(sam9x60_dt, "Microchip SAM9X60")
/* Maintainer: Microchip */
.init_machine = sam9x60_init,
.dt_compat = sam9x60_dt_board_compat,
MACHINE_END
......@@ -691,6 +691,12 @@ static void __init at91_pm_use_default_mode(int pm_mode)
soc_pm.data.suspend_mode = AT91_PM_ULP0;
}
static const struct of_device_id atmel_shdwc_ids[] = {
{ .compatible = "atmel,sama5d2-shdwc" },
{ .compatible = "microchip,sam9x60-shdwc" },
{ /* sentinel. */ }
};
static void __init at91_pm_modes_init(void)
{
struct device_node *np;
......@@ -700,7 +706,7 @@ static void __init at91_pm_modes_init(void)
!at91_is_pm_mode_active(AT91_PM_ULP1))
return;
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc");
np = of_find_matching_node(NULL, atmel_shdwc_ids);
if (!np) {
pr_warn("%s: failed to find shdwc!\n", __func__);
goto ulp1_default;
......@@ -751,6 +757,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
{ .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[1] },
{ /* sentinel */ },
};
......@@ -805,7 +812,7 @@ void __init at91rm9200_pm_init(void)
void __init sam9x60_pm_init(void)
{
if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
return;
at91_pm_modes_init();
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Setup code for SAM9X60.
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
*/
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/system_misc.h>
#include "generic.h"
static void __init sam9x60_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
sam9x60_pm_init();
}
static const char *const sam9x60_dt_board_compat[] __initconst = {
"microchip,sam9x60",
NULL
};
DT_MACHINE_START(sam9x60_dt, "Microchip SAM9X60")
/* Maintainer: Microchip */
.init_machine = sam9x60_init,
.dt_compat = sam9x60_dt_board_compat,
MACHINE_END
......@@ -211,6 +211,7 @@ config ARCH_BRCMSTB
bool "Broadcom BCM7XXX based boards"
depends on ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_GIC
select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER
......
......@@ -3,10 +3,10 @@
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
# Configuration options for the EXYNOS
# Configuration options for the Samsung Exynos
menuconfig ARCH_EXYNOS
bool "Samsung EXYNOS"
bool "Samsung Exynos"
depends on ARCH_MULTI_V7
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SUPPORTS_BIG_ENDIAN
......@@ -42,7 +42,7 @@ menuconfig ARCH_EXYNOS
select POWER_RESET_SYSCON
select POWER_RESET_SYSCON_POWEROFF
help
Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
Support for Samsung Exynos SoCs
if ARCH_EXYNOS
......@@ -52,63 +52,62 @@ config S5P_DEV_MFC
Compile in setup memory (init) code for MFC
config ARCH_EXYNOS3
bool "SAMSUNG EXYNOS3"
bool "Samsung Exynos3"
default y
select ARM_CPU_SUSPEND if PM
help
Samsung EXYNOS3 (Cortex-A7) SoC based systems
Samsung Exynos3 (Cortex-A7) SoC based systems
config ARCH_EXYNOS4
bool "SAMSUNG EXYNOS4"
bool "Samsung Exynos4"
default y
select ARM_CPU_SUSPEND if PM_SLEEP
select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
select CPU_EXYNOS4210
select GIC_NON_BANKED
select MIGHT_HAVE_CACHE_L2X0
help
Samsung EXYNOS4 (Cortex-A9) SoC based systems
Samsung Exynos4 (Cortex-A9) SoC based systems
config ARCH_EXYNOS5
bool "SAMSUNG EXYNOS5"
bool "Samsung Exynos5"
default y
help
Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems
Samsung Exynos5 (Cortex-A15/A7) SoC based systems
comment "EXYNOS SoCs"
comment "Exynos SoCs"
config SOC_EXYNOS3250
bool "SAMSUNG EXYNOS3250"
bool "Samsung Exynos3250"
default y
depends on ARCH_EXYNOS3
config CPU_EXYNOS4210
bool "SAMSUNG EXYNOS4210"
bool "Samsung Exynos4210"
default y
depends on ARCH_EXYNOS4
config SOC_EXYNOS4412
bool "SAMSUNG EXYNOS4412"
bool "Samsung Exynos4412"
default y
depends on ARCH_EXYNOS4
config SOC_EXYNOS5250
bool "SAMSUNG EXYNOS5250"
bool "Samsung Exynos5250"
default y
depends on ARCH_EXYNOS5
config SOC_EXYNOS5260
bool "SAMSUNG EXYNOS5260"
bool "Samsung Exynos5260"
default y
depends on ARCH_EXYNOS5
config SOC_EXYNOS5410
bool "SAMSUNG EXYNOS5410"
bool "Samsung Exynos5410"
default y
depends on ARCH_EXYNOS5
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
bool "Samsung Exynos5420"
default y
depends on ARCH_EXYNOS5
select EXYNOS_MCPM if SMP
......@@ -116,7 +115,7 @@ config SOC_EXYNOS5420
select ARM_CPU_SUSPEND
config SOC_EXYNOS5800
bool "SAMSUNG EXYNOS5800"
bool "Samsung EXYNOS5800"
default y
depends on SOC_EXYNOS5420
......
......@@ -3,7 +3,7 @@
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Common Header for EXYNOS machines
* Common Header for Exynos machines
*/
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
......
// SPDX-License-Identifier: GPL-2.0
//
// SAMSUNG EXYNOS Flattened Device Tree enabled machine
// Samsung Exynos Flattened Device Tree enabled machine
//
// Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com
......@@ -192,7 +192,7 @@ static void __init exynos_dt_fixup(void)
of_fdt_limit_memory(8);
}
DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)")
.l2c_aux_val = 0x3c400001,
.l2c_aux_mask = 0xc20fffff,
.smp = smp_ops(exynos_smp_ops),
......
......@@ -3,7 +3,7 @@
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS - Memory map definitions
* Exynos - Memory map definitions
*/
#ifndef __ASM_ARCH_MAP_H
......
......@@ -3,7 +3,7 @@
// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com
//
// EXYNOS - Power Management support
// Exynos - Power Management support
//
// Based on arch/arm/mach-s3c2410/pm.c
// Copyright (c) 2006 Simtec Electronics
......
......@@ -2,7 +2,7 @@
/*
* Copyright (c) 2012 Samsung Electronics.
*
* EXYNOS - SMC Call
* Exynos - SMC Call
*/
#ifndef __ASM_ARCH_EXYNOS_SMC_H
......
......@@ -3,7 +3,7 @@
// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com
//
// EXYNOS - Suspend support
// Exynos - Suspend support
//
// Based on arch/arm/mach-s3c2410/pm.c
// Copyright (c) 2006 Simtec Electronics
......
......@@ -520,6 +520,7 @@ config SOC_IMX6UL
bool "i.MX6 UltraLite support"
select PINCTRL_IMX6UL
select SOC_IMX6
select ARM_ERRATA_814220
help
This enables support for Freescale i.MX6 UltraLite processor.
......@@ -556,6 +557,7 @@ config SOC_IMX7D
select PINCTRL_IMX7D
select SOC_IMX7D_CA7 if ARCH_MULTI_V7
select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
select ARM_ERRATA_814220 if ARCH_MULTI_V7
help
This enables support for Freescale i.MX7 Dual processor.
......
......@@ -15,6 +15,11 @@
#define OCOTP_UID_H 0x420
#define OCOTP_UID_L 0x410
#define OCOTP_ULP_UID_1 0x4b0
#define OCOTP_ULP_UID_2 0x4c0
#define OCOTP_ULP_UID_3 0x4d0
#define OCOTP_ULP_UID_4 0x4e0
unsigned int __mxc_cpu_type;
static unsigned int imx_soc_revision;
......@@ -164,6 +169,7 @@ struct device * __init imx_soc_device_init(void)
soc_id = "i.MX7D";
break;
case MXC_CPU_IMX7ULP:
ocotp_compat = "fsl,imx7ulp-ocotp";
soc_id = "i.MX7ULP";
break;
default:
......@@ -178,11 +184,25 @@ struct device * __init imx_soc_device_init(void)
}
if (!IS_ERR_OR_NULL(ocotp)) {
regmap_read(ocotp, OCOTP_UID_H, &val);
soc_uid = val;
regmap_read(ocotp, OCOTP_UID_L, &val);
soc_uid <<= 32;
soc_uid |= val;
if (__mxc_cpu_type == MXC_CPU_IMX7ULP) {
regmap_read(ocotp, OCOTP_ULP_UID_4, &val);
soc_uid = val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_3, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_2, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_1, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
} else {
regmap_read(ocotp, OCOTP_UID_H, &val);
soc_uid = val;
regmap_read(ocotp, OCOTP_UID_L, &val);
soc_uid <<= 32;
soc_uid |= val;
}
}
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
......
......@@ -16,11 +16,11 @@ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
clock-common = clock.o
secure-common = omap-smc.o omap-secure.o
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common)
obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
......
......@@ -84,6 +84,15 @@ static struct clockdomain l3s_tsc_43xx_clkdm = {
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain lcdc_43xx_clkdm = {
.name = "lcdc_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.prcm_partition = AM43XX_CM_PARTITION,
.cm_inst = AM43XX_CM_PER_INST,
.clkdm_offs = AM43XX_CM_PER_LCDC_CDOFFS,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain dss_43xx_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "per_pwrdm" },
......@@ -173,6 +182,7 @@ static struct clockdomain *clockdomains_am43xx[] __initdata = {
&pruss_ocp_43xx_clkdm,
&ocpwp_l3_43xx_clkdm,
&l3s_tsc_43xx_clkdm,
&lcdc_43xx_clkdm,
&dss_43xx_clkdm,
&l3_aon_43xx_clkdm,
&emif_43xx_clkdm,
......
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