Commit 8ed607a7 authored by Lokesh Vutla's avatar Lokesh Vutla Committed by Tony Lindgren
Browse files

ARM: dts: AM43xx: clk: Add RNG clk node



Add clk node for RNG module.

Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 610e9c4a
......@@ -104,6 +104,14 @@
clock-div = <1>;
};
rng_fck: rng_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
......
......@@ -58,6 +58,7 @@ static struct ti_dt_clk am43xx_clks[] = {
DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
DT_CLK(NULL, "sha0_fck", "sha0_fck"),
DT_CLK(NULL, "aes0_fck", "aes0_fck"),
DT_CLK(NULL, "rng_fck", "rng_fck"),
DT_CLK(NULL, "timer1_fck", "timer1_fck"),
DT_CLK(NULL, "timer2_fck", "timer2_fck"),
DT_CLK(NULL, "timer3_fck", "timer3_fck"),
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment