Commit cfcbc2db authored by Tony Lindgren's avatar Tony Lindgren
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ARM: dts: Add missing omap4 secure clocks



The secure clocks on omap4 are similar to what we already have for dra7
in dra7_l4sec_clkctrl_regs and documented in the omap4460 TRM "Table
3-1346 L4PER_CM2 Registers Mapping Summary".

The secure clocks are part of the l4_per clock manager. As the l4_per
clock manager has now two clock domains as children, let's also update
the l4_per clockdomain node name to follow the "clock" node naming with
a domain specific compatible property.

Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 6c309052
......@@ -1279,13 +1279,18 @@
#size-cells = <1>;
ranges = <0 0x1400 0x200>;
l4_per_clkctrl: clk@20 {
compatible = "ti,clkctrl";
l4_per_clkctrl: clock@20 {
compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
reg = <0x20 0x144>;
#clock-cells = <2>;
};
};
l4_secure_clkctrl: clock@1a0 {
compatible = "ti,clkctrl-l4-secure", "ti,clkctrl";
reg = <0x1a0 0x3c>;
#clock-cells = <2>;
};
};
};
&prm {
......
......@@ -604,6 +604,18 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
{ 0 },
};
static const struct
omap_clkctrl_reg_data omap4_l4_secure_clkctrl_regs[] __initconst = {
{ OMAP4_AES1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ OMAP4_AES2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ OMAP4_DES3DES_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ OMAP4_PKA_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ OMAP4_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
{ OMAP4_SHA2MD5_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ OMAP4_CRYPTODMA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 0 },
......@@ -691,6 +703,7 @@ const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
{ 0x4a009220, omap4_l3_gfx_clkctrl_regs },
{ 0x4a009320, omap4_l3_init_clkctrl_regs },
{ 0x4a009420, omap4_l4_per_clkctrl_regs },
{ 0x4a0095a0, omap4_l4_secure_clkctrl_regs },
{ 0x4a307820, omap4_l4_wkup_clkctrl_regs },
{ 0x4a307a20, omap4_emu_sys_clkctrl_regs },
{ 0 },
......
......@@ -124,6 +124,17 @@
#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160)
/* l4_secure clocks */
#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0
#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET)
#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0)
#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8)
#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0)
#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8)
#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0)
#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8)
#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8)
/* l4_wkup clocks */
#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
......
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