1. 23 Jan, 2020 27 commits
    • Tony Lindgren's avatar
      ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem · 2256e6f6
      Tony Lindgren authored
      
      
      With "[PATCHv3] w1: omap-hdq: Simplify driver with PM runtime autosuspend"
      we can read the droid4 battery information over 1-wire with this patch
      with something like:
      
      # modprobe omap_hdq
      # hd /sys/bus/w1/devices/89-*/89-*/nvmem
      ...
      
      Unfortunately the format of the battery data seems to be Motorola specific
      and is currently unusable for battery charger unless somebody figures out
      what it means.
      
      Note that currently keeping omap_hdq module loaded will cause extra power
      consumption as it seems to scan devices periodically.
      
      Cc: Merlijn Wajer <merlijn@wizzup.org>
      Cc: Pavel Machek <pavel@ucw.cz>
      Acked-by: default avatarPavel Machek <pavel@ucw.cz>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      2256e6f6
    • Tony Lindgren's avatar
      ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt · 36f808f2
      Tony Lindgren authored
      We added coulomb counter calibration support With commit 0cb90f07
      
      
      ("power: supply: cpcap-battery: Add basic coulomb counter calibrate
      support"), but we also need to configure the related interrupt.
      
      Without the interrupt calibration happens based on a timeout after two
      seconds, with the interrupt the calibration just gets done a bit faster.
      
      Cc: Merlijn Wajer <merlijn@wizzup.org>
      Cc: Pavel Machek <pavel@ucw.cz>
      Acked-by: default avatarPavel Machek <pavel@ucw.cz>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      36f808f2
    • Tony Lindgren's avatar
      ARM: dts: Configure interconnect target module for am437x sgx · a5ebccc8
      Tony Lindgren authored
      
      
      This seems to be similar to what we have for am335x. The following can be
      tested via sysfs with the to ensure the SGX module gets enabled and disabled
      properly:
      
      # echo on > /sys/bus/platform/devices/5600fe00.target-module/power/control
      # rwmem 0x5600fe00              # revision register
      0x5600fe00 = 0x40000000
      # echo auto > /sys/bus/platform/devices/5600fe00.target-module/power/control
      # rwmem 0x5000fe00
      Bus error
      
      Note that this patch depends on the PRM rstctrl driver that has
      been recently posted. If the child device driver(s) need to prevent
      rstctrl reset on PM runtime suspend, the drivers need to increase
      the usecount for the shared rstctrl reset that can be mapped also
      for the child device(s) or accessed via dev->parent.
      
      Cc: Adam Ford <aford173@gmail.com>
      Cc: Filip Matijević <filip.matijevic.pz@gmail.com>
      Cc: "H. Nikolaus Schaller" <hns@goldelico.com>
      Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
      Cc: moaz korena <moaz@korena.xyz>
      Cc: Merlijn Wajer <merlijn@wizzup.org>
      Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
      Cc: Philipp Rossak <embed3d@gmail.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      a5ebccc8
    • Tony Lindgren's avatar
      ARM: dts: Configure sgx for dra7 · 45e118b7
      Tony Lindgren authored
      
      
      I've tested that the interconnect target module enables and idles
      just fine when probed with ti-sysc with PM runtime control via sys:
      
      # echo on > $(find /sys -name control | grep \/5600)
      # rwmem 0x5600fe00      # OCP Revision
      0x5600fe00 = 0x40000000
      # echo auto > $(find /sys -name control | grep \/5600)
      
      Cc: "H. Nikolaus Schaller" <hns@goldelico.com>
      Cc: Robert Nelson <robertcnelson@gmail.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      45e118b7
    • Tony Lindgren's avatar
      ARM: dts: Configure rstctrl reset for am335x SGX · c3fb99f4
      Tony Lindgren authored
      
      
      The following can be tested via sysfs with the following to ensure the SGX
      module gets enabled and disabled properly:
      
      # echo on > /sys/bus/platform/devices/5600fe00.target-module/power/control
      # rwmem 0x5600fe00		# revision register
      0x5600fe00 = 0x40000000
      # echo auto > /sys/bus/platform/devices/5600fe00.target-module/power/control
      # rwmem 0x5000fe00
      Bus error
      
      Note that this patch depends on the PRM rstctrl driver that has
      been recently posted. If the child device driver(s) need to prevent
      rstctrl reset on PM runtime suspend, the drivers need to increase
      the usecount for the shared rstctrl reset that can be mapped also
      for the child device(s) or accessed via dev->parent.
      
      Cc: Adam Ford <aford173@gmail.com>
      Cc: Filip Matijević <filip.matijevic.pz@gmail.com>
      Cc: "H. Nikolaus Schaller" <hns@goldelico.com>
      Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
      Cc: moaz korena <moaz@korena.xyz>
      Cc: Merlijn Wajer <merlijn@wizzup.org>
      Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
      Cc: Philipp Rossak <embed3d@gmail.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      c3fb99f4
    • Benoit Parrot's avatar
      ARM: dts: dra7: Add ti-sysc node for VPE · 1a209516
      Benoit Parrot authored
      
      
      Add VPE node as a child of l4 interconnect in order for it to probe
      using ti-sysc.
      
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      1a209516
    • Benoit Parrot's avatar
      ARM: dts: dra7: add vpe clkctrl node · 79312524
      Benoit Parrot authored
      
      
      Add clkctrl nodes for VPE module.
      
      Note that because of the current dts node name dependency for mapping to
      clock domain, we must still use "vpe-clkctrl@" naming instead of generic
      "clock@" naming for the node. And because of this, it's probably best to
      apply the dts node addition together along with the other clock changes.
      
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Acked-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      79312524
    • Benoit Parrot's avatar
      ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries · d916ab41
      Benoit Parrot authored
      
      
      Add VPFE device nodes entries.
      Add OmniVision OV2659 sensor device nodes and linkage.
      
      Since Rev1.2a on this board the sensor source clock (xvclk) has a
      dedicated 12Mhz oscillator instead of using clkout1.
      Add 'audio_mstrclk' fixed clock object to represent it.
      
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      d916ab41
    • Benoit Parrot's avatar
      ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries · f8404f15
      Benoit Parrot authored
      
      
      Add VPFE device nodes entries.
      Add OmniVision OV2659 sensor device nodes and linkage.
      
      The sensor clock (xvclk) is sourced from clkout1.
      Add clock entries to properly select clkout1 and set its parent
      clock to sys_clkin_ck.
      
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      f8404f15
    • Tero Kristo's avatar
      ARM: dts: am43xx: add support for clkout1 clock · 01053dad
      Tero Kristo authored
      clkout1 clock node and its generation tree was missing. Add this based
      on the data on TRM and PRCM functional spec.
      
      commit 664ae1ab ("ARM: dts: am43xx: add clkctrl nodes") effectively
      reverted this commit 8010f13a ("ARM: dts: am43xx: add support for
      clkout1 clock") which is needed for the ov2659 camera sensor clock
      definition hence it is being re-applied here.
      
      Note that because of the current dts node name dependency for mapping to
      clock domain, we must still use "clkout1-*ck" naming instead of generic
      "clock@" naming for the node. And because of this, it's probably best to
      apply the dts node addition together along with the other clock changes.
      
      Fixes: 664ae1ab
      
       ("ARM: dts: am43xx: add clkctrl nodes")
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      Tested-by: default avatarBenoit Parrot <bparrot@ti.com>
      Acked-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      01053dad
    • Benoit Parrot's avatar
      arm: dts: dra76-evm: Add CAL and OV5640 nodes · 3bd7b487
      Benoit Parrot authored
      
      
      Add device nodes for CSI2 camera board OV5640.
      Add the CAL port nodes with the necessary linkage to the ov5640 nodes.
      
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      3bd7b487
    • Benoit Parrot's avatar
      arm: dtsi: dra76x: Add CAL dtsi node · 80727637
      Benoit Parrot authored
      
      
      Add the required dtsi node to support the Camera
      Adaptation Layer (CAL) for the DRA76 family of devices.
      
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      80727637
    • Benoit Parrot's avatar
      arm: dts: dra72-evm-common: Add entries for the CSI2 cameras · 414dc3d3
      Benoit Parrot authored
      
      
      Add device nodes for CSI2 camera board OV5640.
      Add the CAL port nodes with the necessary linkage to the ov5640 nodes.
      
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      414dc3d3
    • Benoit Parrot's avatar
      ARM: dts: DRA72: Add CAL dtsi node · 86a7e226
      Benoit Parrot authored
      
      
      This patch adds the required dtsi node to support the Camera
      Adaptation Layer (CAL) for the DRA72 family of devices.
      
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      86a7e226
    • Benoit Parrot's avatar
      ARM: dts: dra7-l4: Add ti-sysc node for CAM · b3161725
      Benoit Parrot authored
      
      
      Add CAM nodes as a child of l4 interconnect in order for it to probe
      using ti-sysc.
      
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      b3161725
    • Benoit Parrot's avatar
      ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only · 2baee0c5
      Benoit Parrot authored
      
      
      Both CAL and VIP rely on this clock domain. But CAL DPHY require
      LVDSRX_96M_GFCLK to be active. When this domain is set to HWSUP the
      LVDSRX_96M_GFCLK is on;y active when VIP1 clock is also active.  If only
      CAL on DRA72x (which uses the VIP2 clkctrl) probes the CAM domain is
      enabled but the LVDSRX_96M_GFCLK is left gated. Since LVDSRX_96M_GFCLK
      is sourcing the input clock to the DPHY then actual frame capture cannot
      start as the phy are inactive.
      
      So we either have to also enabled VIP1 even if we don't intend on using
      it or we need to set the CAM domain to use SWSUP only.
      
      This patch implements the latter.
      
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Acked-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      2baee0c5
    • Benoit Parrot's avatar
      ARM: dts: dra7: add cam clkctrl node · 215d103f
      Benoit Parrot authored
      
      
      Add clkctrl nodes for CAM domain.
      
      Note that because of the current dts node name dependency for mapping to
      clock domain, we must still use "cam-clkctrl@" naming instead of generic
      "clock@" naming for the node. And because of this, it's probably best to
      apply the dts node addition together along with the other clock changes.
      
      Signed-off-by: default avatarBenoit Parrot <bparrot@ti.com>
      Acked-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      215d103f
    • Tony Lindgren's avatar
      ARM: OMAP2+: Drop legacy platform data for omap4 des · ddf664da
      Tony Lindgren authored
      
      
      We can now probe devices with ti-sysc interconnect driver and dts
      data. Let's drop the related platform data and custom ti,hwmods
      dts property.
      
      As we're just dropping data, and the early platform data init
      is based on the custom ti,hwmods property, we want to drop both
      the platform data and ti,hwmods property in a single patch.
      
      Cc: Tero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      ddf664da
    • Tony Lindgren's avatar
      ARM: OMAP2+: Drop legacy platform data for omap4 sham · bea5e904
      Tony Lindgren authored
      
      
      We can now probe devices with ti-sysc interconnect driver and dts
      data. Let's drop the related platform data and custom ti,hwmods
      dts property.
      
      As we're just dropping data, and the early platform data init
      is based on the custom ti,hwmods property, we want to drop both
      the platform data and ti,hwmods property in a single patch.
      
      Cc: Tero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      bea5e904
    • Tony Lindgren's avatar
      ARM: OMAP2+: Drop legacy platform data for omap4 aes · 814b2538
      Tony Lindgren authored
      
      
      We can now probe devices with ti-sysc interconnect driver and dts
      data. Let's drop the related platform data and custom ti,hwmods
      dts property.
      
      As we're just dropping data, and the early platform data init
      is based on the custom ti,hwmods property, we want to drop both
      the platform data and ti,hwmods property in a single patch.
      
      Cc: Tero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      814b2538
    • Tony Lindgren's avatar
      ARM: dts: Configure interconnect target module for omap4 des · 23673f17
      Tony Lindgren authored
      
      
      We can now probe devices with device tree only configuration using
      ti-sysc interconnect target module driver. Let's configure the
      module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
      time warnings. The legacy property will be removed in later patches
      together with the legacy platform data.
      
      Cc: Tero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      23673f17
    • Tony Lindgren's avatar
      ARM: dts: Configure interconnect target module for omap4 aes · 316a418e
      Tony Lindgren authored
      
      
      We can now probe devices with device tree only configuration using
      ti-sysc interconnect target module driver. Let's configure the
      module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
      time warnings. The legacy property will be removed in later patches
      together with the legacy platform data.
      
      Cc: Tero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      316a418e
    • Tony Lindgren's avatar
      ARM: dts: Configure interconnect target module for omap4 sham · 18c48e6d
      Tony Lindgren authored
      
      
      We can now probe devices with device tree only configuration using
      ti-sysc interconnect target module driver. Let's configure the
      module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
      time warnings. The legacy property will be removed in later patches
      together with the legacy platform data.
      
      Cc: Tero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      18c48e6d
    • Tony Lindgren's avatar
      ARM: dts: Configure omap5 rng to probe with ti-sysc · 30c2d7ca
      Tony Lindgren authored
      
      
      This is similar to dra7 and omap4 with different clock naming
      and module address.
      
      Cc: devicetree@vger.kernel.org
      Cc: Rob Herring <robh+dt@kernel.org>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      30c2d7ca
    • Tony Lindgren's avatar
      ARM: dts: Configure omap4 rng to probe with ti-sysc · fbb8bb83
      Tony Lindgren authored
      
      
      Add RNG interconnect data for omap4 similar to what dra7 has. The
      clock is OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET at offset address 0x01c0,
      which matches what dra7 also has with DRA7_L4SEC_CLKCTRL_INDEX(0x1c0).
      
      Note that we need to also add the related l4_secure clock entries.
      I've only added RNG, the others can be added as they get tested.
      They are probably very similar to what we already have for dra7
      in dra7_l4sec_clkctrl_regs[].
      
      With the clock tagged CLKF_SOC_NONSEC, clock is set disabled for secure
      devices and clk_get() will fail. Additionally we disable the RNG target
      module on droid4 to avoid introducing new boot time warnings.
      
      Cc: devicetree@vger.kernel.org
      Cc: Rob Herring <robh+dt@kernel.org>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      fbb8bb83
    • Tony Lindgren's avatar
      ARM: dts: Add missing omap5 secure clocks · 723a567f
      Tony Lindgren authored
      
      
      The secure clocks on omap5 are similar to what we already have for dra7
      with dra7_l4sec_clkctrl_regs and documented in the omap5432 TRM in
      "Table 3-1044. CORE_CM_CORE Registers Mapping Summary".
      
      The secure clocks are part of the l4per clock manager. As the l4per
      clock manager has now two clock domains as children, let's also update
      the l4per clockdomain node name to follow the "clock" node naming with
      a domain specific compatible property.
      
      Compared to omap4, omap5 has more clocks working in hardare autogating
      mode.
      
      Cc: devicetree@vger.kernel.org
      Cc: Rob Herring <robh+dt@kernel.org>
      Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      723a567f
    • Tony Lindgren's avatar
      ARM: dts: Add missing omap4 secure clocks · cfcbc2db
      Tony Lindgren authored
      
      
      The secure clocks on omap4 are similar to what we already have for dra7
      in dra7_l4sec_clkctrl_regs and documented in the omap4460 TRM "Table
      3-1346 L4PER_CM2 Registers Mapping Summary".
      
      The secure clocks are part of the l4_per clock manager. As the l4_per
      clock manager has now two clock domains as children, let's also update
      the l4_per clockdomain node name to follow the "clock" node naming with
      a domain specific compatible property.
      
      Cc: devicetree@vger.kernel.org
      Cc: Rob Herring <robh+dt@kernel.org>
      Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      cfcbc2db
  2. 20 Jan, 2020 2 commits
  3. 13 Jan, 2020 2 commits
  4. 30 Dec, 2019 5 commits
  5. 17 Dec, 2019 4 commits