1. 07 Aug, 2019 1 commit
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    • Viresh Kumar's avatar
      ARM/davinci/time: Migrate to new 'set-state' interface · bc660a45
      Viresh Kumar authored
      
      
      Migrate davinci driver to the new 'set-state' interface provided by
      clockevents core, the earlier 'set-mode' interface is marked obsolete
      now.
      
      This also enables us to implement callbacks for new states of clockevent
      devices, for example: ONESHOT_STOPPED.
      
      We weren't doing anything in set_mode(RESUME) and so .tick_resume()
      isn't implemented.
      
      Cc: Sekhar Nori <nsekhar@ti.com>
      Cc: Kevin Hilman <khilman@deeprootsystems.com>
      Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
      bc660a45
  6. 18 Nov, 2014 1 commit
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    • Mark A. Greer's avatar
      davinci: Move PINMUX defines to SoC files · 5570078c
      Mark A. Greer authored
      
      
      Different SoC have different numbers of pinmux registers and other
      resources that overlap with each other.  To clean up the code and
      eliminate defines that overlap with each other, move the PINMUX
      defines to the SoC specific files.
      Signed-off-by: default avatarMark A. Greer <mgreer@mvista.com>
      Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
      5570078c
    • Mark A. Greer's avatar
      davinci: Add compare register support to timer code · 3abd5acf
      Mark A. Greer authored
      
      
      The Timer64p timer has 8 compare registers that can
      be used to generate interrupts when the timer value
      matches the compare reg's value.  They do not disturb
      the timer itself.  This can be useful when there is
      only one timer available for both clock events and
      clocksource.
      
      When enabled, the clocksource remains a continuous
      32-bit counter but the clock event will no longer
      support periodic interrupts.  Instead only oneshot
      timers will be supported and implemented by setting
      the compare register to the current timer value plus
      the period that the clock event subsystem is requesting.
      
      Compare registers support is enabled automatically
      when the following conditions are met:
      1) The same timer is being used for clock events
         and clocksource.
      2) The timer is the bottom half (32 bits) of the
         64-bit timer (hardware limitation).
      3) The the compare register offset and irq are
         not zero.
      
      Since the timer is always running, there is a hardware
      race in timer32_config() between reading the current
      timer value, and adding the period to the current
      timer value and writing the compare register.
      Testing on a da830 evm board with the timer clocked
      at 24 MHz and the processor clocked at 300 MHz,
      showed the number of counter ticks to do this ranged
      from 20-53 (~1-2.2 usecs) but usually around 41 ticks.
      This includes some artifacts from collecting the
      information.  So, the minimum period should be
      at least 5 usecs to be safe.
      
      There is also an non-critical lower limit that
      the period should be since there is no point in
      setting an event that is much shorter than the
      time it takes to set the event, and get & handle
      the timer interrupt for that event.  There can
      also be all sorts of delays from activities
      occuring elsewhere in the system (including
      hardware activitis like cache & TLB management).
      These are virtually impossible to quantify so a
      minimum period of 50 usecs was chosen.  That will
      certianly be enough to avoid the actual hardware
      race but hopefully not large enough to cause
      unreasonably course-grained timers.
      Signed-off-by: default avatarMark A. Greer <mgreer@mvista.com>
      Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
      3abd5acf
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