1. 06 Nov, 2020 1 commit
  2. 28 Oct, 2020 1 commit
    • Arnd Bergmann's avatar
      arm64: avoid -Woverride-init warning · 332576e6
      Arnd Bergmann authored
      The icache_policy_str[] definition causes a warning when extra
      warning flags are enabled:
      
      arch/arm64/kernel/cpuinfo.c:38:26: warning: initialized field overwritten [-Woverride-init]
         38 |  [ICACHE_POLICY_VIPT]  = "VIPT",
            |                          ^~~~~~
      arch/arm64/kernel/cpuinfo.c:38:26: note: (near initialization for 'icache_policy_str[2]')
      arch/arm64/kernel/cpuinfo.c:39:26: warning: initialized field overwritten [-Woverride-init]
         39 |  [ICACHE_POLICY_PIPT]  = "PIPT",
            |                          ^~~~~~
      arch/arm64/kernel/cpuinfo.c:39:26: note: (near initialization for 'icache_policy_str[3]')
      arch/arm64/kernel/cpuinfo.c:40:27: warning: initialized field overwritten [-Woverride-init]
         40 |  [ICACHE_POLICY_VPIPT]  = "VPIPT",
            |                           ^~~~~~~
      arch/arm64/kernel/cpuinfo.c:40:27: note: (near initialization for 'icache_policy_str[0]')
      
      There is no real need for the default initializer here, as printing a
      NULL string is harmless. Rewrite the logic to have an explicit
      reserved value for the only one that uses the default value.
      
      This partially reverts the commit that removed ICACHE_POLICY_AIVIVT.
      
      Fixes: 155433cb
      
       ("arm64: cache: Remove support for ASID-tagged VIVT I-caches")
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Link: https://lore.kernel.org/r/20201026193807.3816388-1-arnd@kernel.org
      
      
      Signed-off-by: default avatarWill Deacon <will@kernel.org>
      332576e6
  3. 25 Oct, 2020 1 commit
  4. 22 Feb, 2020 1 commit
  5. 25 Oct, 2019 1 commit
  6. 13 Aug, 2019 1 commit
  7. 19 Jun, 2019 1 commit
  8. 17 Jun, 2019 1 commit
  9. 04 Jun, 2019 1 commit
  10. 16 Jan, 2019 1 commit
  11. 09 Jan, 2019 1 commit
  12. 16 Oct, 2018 1 commit
    • Suzuki Poulose's avatar
      arm64: cpufeature: Fix handling of CTR_EL0.IDC field · 1602df02
      Suzuki Poulose authored and Catalin Marinas's avatar Catalin Marinas committed
      CTR_EL0.IDC reports the data cache clean requirements for instruction
      to data coherence. However, if the field is 0, we need to check the
      CLIDR_EL1 fields to detect the status of the feature. Currently we
      don't do this and generate a warning with tainting the kernel, when
      there is a mismatch in the field among the CPUs. Also the userspace
      doesn't have a reliable way to check the CLIDR_EL1 register to check
      the status.
      
      This patch fixes the problem by checking the CLIDR_EL1 fields, when
      (CTR_EL0.IDC == 0) and updates the kernel's copy of the CTR_EL0 for
      the CPU with the actual status of the feature. This would allow the
      sanity check infrastructure to do the proper checking of the fields
      and also allow the CTR_EL0 emulation code to supply the real status
      of the feature.
      
      Now, if a CPU has raw CTR_EL0.IDC == 0 and effective IDC == 1 (with
      overall system wide IDC == 1), we need to expose the real value to
      the user. So, we trap CTR_EL0 access on the CPU which reports incorrect
      CTR_EL0.IDC.
      
      Fixes: commit 6ae4b6e0
      
       ("arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC")
      Cc: Shanker Donthineni <shankerd@codeaurora.org>
      Cc: Philip Elcan <pelcan@codeaurora.org>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: Suzuki Poulose's avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: Catalin Marinas's avatarCatalin Marinas <catalin.marinas@arm.com>
      1602df02
  13. 05 Jul, 2018 1 commit
    • Suzuki Poulose's avatar
      arm64: Fix mismatched cache line size detection · 4c4a39dd
      Suzuki Poulose authored
      If there is a mismatch in the I/D min line size, we must
      always use the system wide safe value both in applications
      and in the kernel, while performing cache operations. However,
      we have been checking more bits than just the min line sizes,
      which triggers false negatives. We may need to trap the user
      accesses in such cases, but not necessarily patch the kernel.
      
      This patch fixes the check to do the right thing as advertised.
      A new capability will be added to check mismatches in other
      fields and ensure we trap the CTR accesses.
      
      Fixes: be68a8aa
      
       ("arm64: cpufeature: Fix CTR_EL0 field definitions")
      Cc: <stable@vger.kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Reported-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: Suzuki Poulose's avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      4c4a39dd
  14. 15 May, 2018 1 commit
    • Catalin Marinas's avatar
      arm64: Increase ARCH_DMA_MINALIGN to 128 · ebc7e21e
      Catalin Marinas authored
      
      
      This patch increases the ARCH_DMA_MINALIGN to 128 so that it covers the
      currently known Cache Writeback Granule (CTR_EL0.CWG) on arm64 and moves
      the fallback in cache_line_size() from L1_CACHE_BYTES to this constant.
      In addition, it warns (and taints) if the CWG is larger than
      ARCH_DMA_MINALIGN as this is not safe with non-coherent DMA.
      
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Robin Murphy <robin.murphy@arm.com>
      Signed-off-by: Catalin Marinas's avatarCatalin Marinas <catalin.marinas@arm.com>
      ebc7e21e
  15. 11 May, 2018 1 commit
    • Catalin Marinas's avatar
      Revert "arm64: Increase the max granular size" · d93277b9
      Catalin Marinas authored
      This reverts commit 97303480.
      
      Commit 97303480
      
       ("arm64: Increase the max granular size") increased
      the cache line size to 128 to match Cavium ThunderX, apparently for some
      performance benefit which could not be confirmed. This change, however,
      has an impact on the network packet allocation in certain circumstances,
      requiring slightly over a 4K page with a significant performance
      degradation. The patch reverts L1_CACHE_SHIFT back to 6 (64-byte cache
      line).
      
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Robin Murphy <robin.murphy@arm.com>
      Signed-off-by: Catalin Marinas's avatarCatalin Marinas <catalin.marinas@arm.com>
      d93277b9
  16. 27 Mar, 2018 1 commit
  17. 09 Mar, 2018 1 commit
    • Shanker Donthineni's avatar
      arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC · 6ae4b6e0
      Shanker Donthineni authored
      
      
      The DCache clean & ICache invalidation requirements for instructions
      to be data coherence are discoverable through new fields in CTR_EL0.
      The following two control bits DIC and IDC were defined for this
      purpose. No need to perform point of unification cache maintenance
      operations from software on systems where CPU caches are transparent.
      
      This patch optimize the three functions __flush_cache_user_range(),
      clean_dcache_area_pou() and invalidate_icache_range() if the hardware
      reports CTR_EL0.IDC and/or CTR_EL0.IDC. Basically it skips the two
      instructions 'DC CVAU' and 'IC IVAU', and the associated loop logic
      in order to avoid the unnecessary overhead.
      
      CTR_EL0.DIC: Instruction cache invalidation requirements for
       instruction to data coherence. The meaning of this bit[29].
        0: Instruction cache invalidation to the point of unification
           is required for instruction to data coherence.
        1: Instruction cache cleaning to the point of unification is
            not required for instruction to data coherence.
      
      CTR_EL0.IDC: Data cache clean requirements for instruction to data
       coherence. The meaning of this bit[28].
        0: Data cache clean to the point of unification is required for
           instruction to data coherence, unless CLIDR_EL1.LoC == 0b000
           or (CLIDR_EL1.LoUIS == 0b000 && CLIDR_EL1.LoUU == 0b000).
        1: Data cache clean to the point of unification is not required
           for instruction to data coherence.
      
      Co-authored-by: default avatarPhilip Elcan <pelcan@codeaurora.org>
      Reviewed-by: Mark Rutland's avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarShanker Donthineni <shankerd@codeaurora.org>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      6ae4b6e0
  18. 06 Mar, 2018 1 commit
    • Catalin Marinas's avatar
      arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size) · 1f85b42a
      Catalin Marinas authored
      Commit 97303480
      
       ("arm64: Increase the max granular size") increased
      the cache line size to 128 to match Cavium ThunderX, apparently for some
      performance benefit which could not be confirmed. This change, however,
      has an impact on the network packets allocation in certain
      circumstances, requiring slightly over a 4K page with a significant
      performance degradation.
      
      This patch reverts L1_CACHE_SHIFT back to 6 (64-byte cache line) while
      keeping ARCH_DMA_MINALIGN at 128. The cache_line_size() function was
      changed to default to ARCH_DMA_MINALIGN in the absence of a meaningful
      CTR_EL0.CWG bit field.
      
      In addition, if a system with ARCH_DMA_MINALIGN < CTR_EL0.CWG is
      detected, the kernel will force swiotlb bounce buffering for all
      non-coherent devices since DMA cache maintenance on sub-CWG ranges is
      not safe, leading to data corruption.
      
      Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com>
      Cc: Timur Tabi <timur@codeaurora.org>
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Acked-by: Robin Murphy's avatarRobin Murphy <robin.murphy@arm.com>
      Signed-off-by: Catalin Marinas's avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      1f85b42a
  19. 20 Mar, 2017 2 commits
  20. 28 Oct, 2015 1 commit
  21. 03 Dec, 2014 1 commit
  22. 09 May, 2014 1 commit
  23. 17 Sep, 2012 3 commits
  24. 17 Jul, 2007 1 commit
  25. 19 Jun, 2006 1 commit
  26. 09 Jan, 2006 2 commits
  27. 16 Nov, 2005 1 commit
  28. 16 Apr, 2005 1 commit
    • Linus Torvalds's avatar
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds authored
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4