• Jim Quinlan's avatar
    MIPS: Make local_irq_disable macro safe for non-Mipsr2 · 71ca7588
    Jim Quinlan authored
    For non-mipsr2 processors, the local_irq_disable contains an mfc0-mtc0
    pair with instructions inbetween.  With preemption enabled, this sequence
    may get preempted and effect a stale value of CP0_STATUS when executing
    the mtc0 instruction.  This commit avoids this scenario by incrementing
    the preempt count before the mfc0 and decrementing it after the mtc9.
    [ralf@linux-mips.org: This patch is sorting out the part that were missed
    by e97c5b60
     [MIPS: Make irqflags.h functions preempt-safe for non-mipsr2
    cpus.]  I also re-enabled the inclusion of <asm/asm-offsets.h> at the top
    of <asm/asmmacro.h>].
    Signed-off-by: default avatarJim Quinlan <jim2101024@gmail.com>
    Cc: linux-mips@linux-mips.org
    Cc: cernekee@gmail.com
    Patchwork: https://patchwork.linux-mips.org/patch/6164/
    Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>