• John David Anglin's avatar
    parisc: Also flush data TLB in flush_icache_page_asm · 5035b230
    John David Anglin authored
    
    
    This is the second issue I noticed in reviewing the parisc TLB code.
    
    The fic instruction may use either the instruction or data TLB in
    flushing the instruction cache.  Thus, on machines with a split TLB, we
    should also flush the data TLB after setting up the temporary alias
    registers.
    
    Although this has no functional impact, I changed the pdtlb and pitlb
    instructions to consistently use the index register %r0.  These
    instructions do not support integer displacements.
    
    Tested on rp3440 and c8000.
    Signed-off-by: default avatarJohn David Anglin  <dave.anglin@bell.net>
    Cc: <stable@vger.kernel.org> # v3.16+
    Signed-off-by: default avatarHelge Deller <deller@gmx.de>
    5035b230
pacache.S 29.9 KB