1. 25 Nov, 2016 1 commit
    • John David Anglin's avatar
      parisc: Also flush data TLB in flush_icache_page_asm · 5035b230
      John David Anglin authored
      
      
      This is the second issue I noticed in reviewing the parisc TLB code.
      
      The fic instruction may use either the instruction or data TLB in
      flushing the instruction cache.  Thus, on machines with a split TLB, we
      should also flush the data TLB after setting up the temporary alias
      registers.
      
      Although this has no functional impact, I changed the pdtlb and pitlb
      instructions to consistently use the index register %r0.  These
      instructions do not support integer displacements.
      
      Tested on rp3440 and c8000.
      Signed-off-by: default avatarJohn David Anglin  <dave.anglin@bell.net>
      Cc: <stable@vger.kernel.org> # v3.16+
      Signed-off-by: default avatarHelge Deller <deller@gmx.de>
      5035b230
  2. 05 Oct, 2016 1 commit
  3. 20 Sep, 2016 1 commit
  4. 18 Jun, 2013 1 commit
  5. 24 May, 2013 1 commit
  6. 06 May, 2013 1 commit
    • Helge Deller's avatar
      parisc: fix partly 16/64k PAGE_SIZE boot · 6a45716a
      Helge Deller authored
      
      
      This patch fixes partly PAGE_SIZEs of 16K or 64K by adjusting the
      assembler PTE lookup code and the assembler TEMPALIAS code.  Furthermore
      some data alignments for PAGE_SIZE have been limited to 4K (or less) to
      not waste too much memory with greater page sizes. As a side note, the
      palo loader can (currently) only handle up to 10 ELF segments which is
      fixed with tighter aligning as well.
      
      My testings indicated that the ldci command in the sba iommu coding
      needed adjustment by the PAGE_SHIFT value and that the I/O PDIR Page
      size was only set to 4K for my machine (C3000).
      
      All this fixes partly the boot, but there are still quite some caching
      problems left.  Examples are e.g. the symbios logic driver which is
      failing:
      
      sym0: <896> rev 0x7 at pci 0000:00:0f.0 irq 69
      sym0: PA-RISC Firmware, ID 7, Fast-40, SE, parity checking
      CACHE TEST FAILED: DMA error (dstat=0x81).sym0: CACHE INCORRECTLY CONFIGURED.
      
      and the tulip network driver which doesn't seem to work correctly
      either:
      
      Sending BOOTP requests .net eth0: Setting full-duplex based on MII#1
      link partner capability of 05e1
      ..... timed out!
      
      Beside those kernel fixes glibc will need fixes too to be able to handle
      >4K page sizes.
      Signed-off-by: default avatarHelge Deller <deller@gmx.de>
      6a45716a
  7. 20 Feb, 2013 1 commit
    • John David Anglin's avatar
      parisc: fixes and cleanups in page cache flushing (2/4) · 6d2ddc2f
      John David Anglin authored
      
      
      Implement clear_page_asm and copy_page_asm. These are optimized routines to
      clear and copy a page.  I tested prefetch optimizations in clear_page_asm and
      copy_page_asm but didn't see any significant performance improvement on rp3440.
      I'm not sure if these are routines are significantly faster than memset and/or
      memcpy, but they are there for further performance evaluation.
      
      TLB purge operations on PA 1.X SMP machines are now serialized with the help of
      the new tlb_lock() and tlb_unlock() macros, since on some PA-RISC machines, TLB
      purges need to be serialized in software.  Obviously, lock isn't needed in UP
      kernels.  On PA 2.0 machines, there is a local TLB instruction which is much
      less disruptive to the memory subsystem.  No lock is needed for local purge.
      
      Loops are also unrolled in flush_instruction_cache_local and
      flush_data_cache_local.
      
      The implementation of what used to be copy_user_page (now copy_user_page_asm)
      is now fixed. Additionally 64-bit support is now added. Read the preceding
      comment which I didn't change.  I left the comment but it is now inaccurate.
      Signed-off-by: default avatarJohn David Anglin <dave.anglin@bell.net>
      Signed-off-by: default avatarHelge Deller <deller@gmx.de>
      6d2ddc2f
  8. 16 May, 2012 1 commit
  9. 15 Apr, 2011 1 commit
  10. 15 Jan, 2011 1 commit
    • James Bottomley's avatar
      parisc: flush pages through tmpalias space · f311847c
      James Bottomley authored
      
      
      The kernel has an 8M tmpailas space (originally designed for copying
      and clearing pages but now only used for clearing).  The idea is
      to place zeros into the cache above a physical page rather than into
      the physical page and flush the cache, because often the zeros end up
      being replaced quickly anyway.
      
      We can also use the tmpalias space for flushing a page.  The difference
      here is that we have to do tmpalias processing in the non access data and
      instruction traps.  The principle is the same: as long as we know the physical
      address and have a virtual address congruent to the real one, the flush will
      be effective.
      
      In order to use the tmpalias space, the icache miss path has to be enhanced to
      check for the alias region to make the fic instruction effective.
      Signed-off-by: default avatarJames Bottomley <James.Bottomley@suse.de>
      f311847c
  11. 13 Jun, 2008 1 commit
  12. 15 May, 2008 2 commits
  13. 18 Oct, 2007 1 commit
  14. 17 Feb, 2007 2 commits
  15. 30 Jun, 2006 1 commit
  16. 21 Apr, 2006 1 commit
  17. 30 Mar, 2006 1 commit
  18. 22 Oct, 2005 5 commits
  19. 16 Apr, 2005 1 commit
    • Linus Torvalds's avatar
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds authored
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4