amd_iommu_init.c 77.1 KB
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
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 * Author: Joerg Roedel <jroedel@suse.de>
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 *         Leo Duran <leo.duran@amd.com>
 */

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#define pr_fmt(fmt)     "AMD-Vi: " fmt
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#define dev_fmt(fmt)    pr_fmt(fmt)
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#include <linux/pci.h>
#include <linux/acpi.h>
#include <linux/list.h>
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#include <linux/bitmap.h>
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <linux/interrupt.h>
#include <linux/msi.h>
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#include <linux/amd-iommu.h>
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#include <linux/export.h>
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#include <linux/iommu.h>
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#include <linux/kmemleak.h>
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#include <linux/mem_encrypt.h>
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#include <asm/pci-direct.h>
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#include <asm/iommu.h>
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#include <asm/apic.h>
#include <asm/msidef.h>
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#include <asm/gart.h>
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#include <asm/x86_init.h>
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#include <asm/iommu_table.h>
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#include <asm/io_apic.h>
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#include <asm/irq_remapping.h>
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#include <linux/crash_dump.h>
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#include "amd_iommu.h"
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#include "amd_iommu_proto.h"
#include "amd_iommu_types.h"
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#include "irq_remapping.h"
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/*
 * definitions for the ACPI scanning code
 */
#define IVRS_HEADER_LENGTH 48

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#define ACPI_IVHD_TYPE_MAX_SUPPORTED	0x40
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#define ACPI_IVMD_TYPE_ALL              0x20
#define ACPI_IVMD_TYPE                  0x21
#define ACPI_IVMD_TYPE_RANGE            0x22

#define IVHD_DEV_ALL                    0x01
#define IVHD_DEV_SELECT                 0x02
#define IVHD_DEV_SELECT_RANGE_START     0x03
#define IVHD_DEV_RANGE_END              0x04
#define IVHD_DEV_ALIAS                  0x42
#define IVHD_DEV_ALIAS_RANGE            0x43
#define IVHD_DEV_EXT_SELECT             0x46
#define IVHD_DEV_EXT_SELECT_RANGE       0x47
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#define IVHD_DEV_SPECIAL		0x48
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#define IVHD_DEV_ACPI_HID		0xf0
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#define UID_NOT_PRESENT                 0
#define UID_IS_INTEGER                  1
#define UID_IS_CHARACTER                2

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#define IVHD_SPECIAL_IOAPIC		1
#define IVHD_SPECIAL_HPET		2
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#define IVHD_FLAG_HT_TUN_EN_MASK        0x01
#define IVHD_FLAG_PASSPW_EN_MASK        0x02
#define IVHD_FLAG_RESPASSPW_EN_MASK     0x04
#define IVHD_FLAG_ISOC_EN_MASK          0x08
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#define IVMD_FLAG_EXCL_RANGE            0x08
#define IVMD_FLAG_UNITY_MAP             0x01

#define ACPI_DEVFLAG_INITPASS           0x01
#define ACPI_DEVFLAG_EXTINT             0x02
#define ACPI_DEVFLAG_NMI                0x04
#define ACPI_DEVFLAG_SYSMGT1            0x10
#define ACPI_DEVFLAG_SYSMGT2            0x20
#define ACPI_DEVFLAG_LINT0              0x40
#define ACPI_DEVFLAG_LINT1              0x80
#define ACPI_DEVFLAG_ATSDIS             0x10000000

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#define LOOP_TIMEOUT	100000
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/*
 * ACPI table definitions
 *
 * These data structures are laid over the table to parse the important values
 * out of it.
 */

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extern const struct iommu_ops amd_iommu_ops;

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/*
 * structure describing one IOMMU in the ACPI table. Typically followed by one
 * or more ivhd_entrys.
 */
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struct ivhd_header {
	u8 type;
	u8 flags;
	u16 length;
	u16 devid;
	u16 cap_ptr;
	u64 mmio_phys;
	u16 pci_seg;
	u16 info;
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	u32 efr_attr;

	/* Following only valid on IVHD type 11h and 40h */
	u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
	u64 res;
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} __attribute__((packed));

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/*
 * A device entry describing which devices a specific IOMMU translates and
 * which requestor ids they use.
 */
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struct ivhd_entry {
	u8 type;
	u16 devid;
	u8 flags;
	u32 ext;
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	u32 hidh;
	u64 cid;
	u8 uidf;
	u8 uidl;
	u8 uid;
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} __attribute__((packed));

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/*
 * An AMD IOMMU memory definition structure. It defines things like exclusion
 * ranges for devices and regions that should be unity mapped.
 */
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struct ivmd_header {
	u8 type;
	u8 flags;
	u16 length;
	u16 devid;
	u16 aux;
	u64 resv;
	u64 range_start;
	u64 range_length;
} __attribute__((packed));

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bool amd_iommu_dump;
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bool amd_iommu_irq_remap __read_mostly;
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int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
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static int amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
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static bool amd_iommu_detected;
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static bool __initdata amd_iommu_disabled;
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static int amd_iommu_target_ivhd_type;
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u16 amd_iommu_last_bdf;			/* largest PCI device id we have
					   to handle */
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LIST_HEAD(amd_iommu_unity_map);		/* a list of required unity mappings
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					   we find in ACPI */
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bool amd_iommu_unmap_flush;		/* if true, flush on every unmap */
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LIST_HEAD(amd_iommu_list);		/* list of all AMD IOMMUs in the
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					   system */
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/* Array to assign indices to IOMMUs*/
struct amd_iommu *amd_iommus[MAX_IOMMUS];
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/* Number of IOMMUs present in the system */
static int amd_iommus_present;
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/* IOMMUs have a non-present cache? */
bool amd_iommu_np_cache __read_mostly;
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bool amd_iommu_iotlb_sup __read_mostly = true;
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u32 amd_iommu_max_pasid __read_mostly = ~0;
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bool amd_iommu_v2_present __read_mostly;
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static bool amd_iommu_pc_present __read_mostly;
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bool amd_iommu_force_isolation __read_mostly;

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/*
 * Pointer to the device table which is shared by all AMD IOMMUs
 * it is indexed by the PCI device id or the HT unit id and contains
 * information about the domain the device belongs to as well as the
 * page table root pointer.
 */
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struct dev_table_entry *amd_iommu_dev_table;
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/*
 * Pointer to a device table which the content of old device table
 * will be copied to. It's only be used in kdump kernel.
 */
static struct dev_table_entry *old_dev_tbl_cpy;
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/*
 * The alias table is a driver specific data structure which contains the
 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
 * More than one device can share the same requestor id.
 */
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u16 *amd_iommu_alias_table;
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/*
 * The rlookup table is used to find the IOMMU which is responsible
 * for a specific device. It is also indexed by the PCI device id.
 */
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struct amd_iommu **amd_iommu_rlookup_table;
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EXPORT_SYMBOL(amd_iommu_rlookup_table);
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/*
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 * This table is used to find the irq remapping table for a given device id
 * quickly.
 */
struct irq_remap_table **irq_lookup_table;

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/*
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 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
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 * to know which ones are already in use.
 */
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unsigned long *amd_iommu_pd_alloc_bitmap;

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static u32 dev_table_size;	/* size of the device table */
static u32 alias_table_size;	/* size of the alias table */
static u32 rlookup_table_size;	/* size if the rlookup table */
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enum iommu_init_state {
	IOMMU_START_STATE,
	IOMMU_IVRS_DETECTED,
	IOMMU_ACPI_FINISHED,
	IOMMU_ENABLED,
	IOMMU_PCI_INIT,
	IOMMU_INTERRUPTS_EN,
	IOMMU_DMA_OPS,
	IOMMU_INITIALIZED,
	IOMMU_NOT_FOUND,
	IOMMU_INIT_ERROR,
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	IOMMU_CMDLINE_DISABLED,
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};

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/* Early ioapic and hpet maps from kernel command line */
#define EARLY_MAP_SIZE		4
static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
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static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];

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static int __initdata early_ioapic_map_size;
static int __initdata early_hpet_map_size;
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static int __initdata early_acpihid_map_size;

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static bool __initdata cmdline_maps;
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static enum iommu_init_state init_state = IOMMU_START_STATE;

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static int amd_iommu_enable_interrupts(void);
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static int __init iommu_go_to_state(enum iommu_init_state state);
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static void init_device_table_dma(void);
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static bool amd_iommu_pre_enabled = true;
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bool translation_pre_enabled(struct amd_iommu *iommu)
{
	return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);
}
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EXPORT_SYMBOL(translation_pre_enabled);
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static void clear_translation_pre_enabled(struct amd_iommu *iommu)
{
	iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
}

static void init_translation_status(struct amd_iommu *iommu)
{
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	u64 ctrl;
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	ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
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	if (ctrl & (1<<CONTROL_IOMMU_EN))
		iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
}

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static inline void update_last_devid(u16 devid)
{
	if (devid > amd_iommu_last_bdf)
		amd_iommu_last_bdf = devid;
}

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static inline unsigned long tbl_size(int entry_size)
{
	unsigned shift = PAGE_SHIFT +
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			 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
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	return 1UL << shift;
}

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int amd_iommu_get_num_iommus(void)
{
	return amd_iommus_present;
}

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/* Access to l1 and l2 indexed register spaces */

static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
{
	u32 val;

	pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
	pci_read_config_dword(iommu->dev, 0xfc, &val);
	return val;
}

static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
{
	pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
	pci_write_config_dword(iommu->dev, 0xfc, val);
	pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
}

static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
{
	u32 val;

	pci_write_config_dword(iommu->dev, 0xf0, address);
	pci_read_config_dword(iommu->dev, 0xf4, &val);
	return val;
}

static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
{
	pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
	pci_write_config_dword(iommu->dev, 0xf4, val);
}

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/****************************************************************************
 *
 * AMD IOMMU MMIO register space handling functions
 *
 * These functions are used to program the IOMMU device registers in
 * MMIO space required for that driver.
 *
 ****************************************************************************/
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/*
 * This function set the exclusion range in the IOMMU. DMA accesses to the
 * exclusion range are passed through untranslated
 */
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static void iommu_set_exclusion_range(struct amd_iommu *iommu)
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{
	u64 start = iommu->exclusion_start & PAGE_MASK;
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	u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK;
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	u64 entry;

	if (!iommu->exclusion_start)
		return;

	entry = start | MMIO_EXCL_ENABLE_MASK;
	memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
			&entry, sizeof(entry));

	entry = limit;
	memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
			&entry, sizeof(entry));
}

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/* Programs the physical address of the device table into the IOMMU hardware */
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static void iommu_set_device_table(struct amd_iommu *iommu)
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{
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	u64 entry;
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	BUG_ON(iommu->mmio_base == NULL);

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	entry = iommu_virt_to_phys(amd_iommu_dev_table);
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	entry |= (dev_table_size >> 12) - 1;
	memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
			&entry, sizeof(entry));
}

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/* Generic functions to enable/disable certain features of the IOMMU. */
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static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
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{
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	u64 ctrl;
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	ctrl = readq(iommu->mmio_base +  MMIO_CONTROL_OFFSET);
	ctrl |= (1ULL << bit);
	writeq(ctrl, iommu->mmio_base +  MMIO_CONTROL_OFFSET);
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}

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static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
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{
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	u64 ctrl;
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	ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
	ctrl &= ~(1ULL << bit);
	writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
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}

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static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
{
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	u64 ctrl;
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	ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
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	ctrl &= ~CTRL_INV_TO_MASK;
	ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
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	writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
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}

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/* Function to enable the hardware */
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static void iommu_enable(struct amd_iommu *iommu)
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{
	iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
}

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static void iommu_disable(struct amd_iommu *iommu)
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{
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	if (!iommu->mmio_base)
		return;

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	/* Disable command buffer */
	iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);

	/* Disable event logging and event interrupts */
	iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
	iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);

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	/* Disable IOMMU GA_LOG */
	iommu_feature_disable(iommu, CONTROL_GALOG_EN);
	iommu_feature_disable(iommu, CONTROL_GAINT_EN);

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	/* Disable IOMMU hardware itself */
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	iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
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}

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/*
 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
 * the system has one.
 */
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static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
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{
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	if (!request_mem_region(address, end, "amd_iommu")) {
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		pr_err("Can not reserve memory region %llx-%llx for mmio\n",
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			address, end);
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		pr_err("This is a BIOS bug. Please contact your hardware vendor\n");
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		return NULL;
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	}
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	return (u8 __iomem *)ioremap_nocache(address, end);
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}

static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
{
	if (iommu->mmio_base)
		iounmap(iommu->mmio_base);
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	release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
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}

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static inline u32 get_ivhd_header_size(struct ivhd_header *h)
{
	u32 size = 0;

	switch (h->type) {
	case 0x10:
		size = 24;
		break;
	case 0x11:
	case 0x40:
		size = 40;
		break;
	}
	return size;
}

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/****************************************************************************
 *
 * The functions below belong to the first pass of AMD IOMMU ACPI table
 * parsing. In this pass we try to find out the highest device id this
 * code has to handle. Upon this information the size of the shared data
 * structures is determined later.
 *
 ****************************************************************************/

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/*
 * This function calculates the length of a given IVHD entry
 */
static inline int ivhd_entry_length(u8 *ivhd)
{
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	u32 type = ((struct ivhd_entry *)ivhd)->type;

	if (type < 0x80) {
		return 0x04 << (*ivhd >> 6);
	} else if (type == IVHD_DEV_ACPI_HID) {
		/* For ACPI_HID, offset 21 is uid len */
		return *((u8 *)ivhd + 21) + 22;
	}
	return 0;
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}

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/*
 * After reading the highest device id from the IOMMU PCI capability header
 * this function looks if there is a higher device id defined in the ACPI table
 */
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static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
{
	u8 *p = (void *)h, *end = (void *)h;
	struct ivhd_entry *dev;

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	u32 ivhd_size = get_ivhd_header_size(h);

	if (!ivhd_size) {
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		pr_err("Unsupported IVHD type %#x\n", h->type);
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		return -EINVAL;
	}

	p += ivhd_size;
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	end += h->length;

	while (p < end) {
		dev = (struct ivhd_entry *)p;
		switch (dev->type) {
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		case IVHD_DEV_ALL:
			/* Use maximum BDF value for DEV_ALL */
			update_last_devid(0xffff);
			break;
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		case IVHD_DEV_SELECT:
		case IVHD_DEV_RANGE_END:
		case IVHD_DEV_ALIAS:
		case IVHD_DEV_EXT_SELECT:
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			/* all the above subfield types refer to device ids */
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			update_last_devid(dev->devid);
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			break;
		default:
			break;
		}
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		p += ivhd_entry_length(p);
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	}

	WARN_ON(p != end);

	return 0;
}

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static int __init check_ivrs_checksum(struct acpi_table_header *table)
{
	int i;
	u8 checksum = 0, *p = (u8 *)table;

	for (i = 0; i < table->length; ++i)
		checksum += p[i];
	if (checksum != 0) {
		/* ACPI table corrupt */
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		pr_err(FW_BUG "IVRS invalid checksum\n");
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		return -ENODEV;
	}

	return 0;
}

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/*
 * Iterate over all IVHD entries in the ACPI table and find the highest device
 * id which we need to handle. This is the first of three functions which parse
 * the ACPI table. So we check the checksum here.
 */
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static int __init find_last_devid_acpi(struct acpi_table_header *table)
{
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	u8 *p = (u8 *)table, *end = (u8 *)table;
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	struct ivhd_header *h;

	p += IVRS_HEADER_LENGTH;

	end += table->length;
	while (p < end) {
		h = (struct ivhd_header *)p;
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		if (h->type == amd_iommu_target_ivhd_type) {
			int ret = find_last_devid_from_ivhd(h);

			if (ret)
				return ret;
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		}
		p += h->length;
	}
	WARN_ON(p != end);

	return 0;
}

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/****************************************************************************
 *
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Frank Arnold committed
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 * The following functions belong to the code path which parses the ACPI table
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 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
 * data structures, initialize the device/alias/rlookup table and also
 * basically initialize the hardware.
 *
 ****************************************************************************/

/*
 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
 * write commands to that buffer later and the IOMMU will execute them
 * asynchronously
 */
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static int __init alloc_command_buffer(struct amd_iommu *iommu)
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{
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	iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
						  get_order(CMD_BUFFER_SIZE));
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	return iommu->cmd_buf ? 0 : -ENOMEM;
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}

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/*
 * This function resets the command buffer if the IOMMU stopped fetching
 * commands from it.
 */
void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
{
	iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);

	writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
	writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
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	iommu->cmd_buf_head = 0;
	iommu->cmd_buf_tail = 0;
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	iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
}

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/*
 * This function writes the command buffer address to the hardware and
 * enables it.
 */
static void iommu_enable_command_buffer(struct amd_iommu *iommu)
{
	u64 entry;

	BUG_ON(iommu->cmd_buf == NULL);

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	entry = iommu_virt_to_phys(iommu->cmd_buf);
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	entry |= MMIO_CMD_SIZE_512;
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	memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
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		    &entry, sizeof(entry));
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	amd_iommu_reset_cmd_buffer(iommu);
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}

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/*
 * This function disables the command buffer
 */
static void iommu_disable_command_buffer(struct amd_iommu *iommu)
{
	iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
}

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static void __init free_command_buffer(struct amd_iommu *iommu)
{
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	free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
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}

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/* allocates the memory where the IOMMU will log its events to */
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static int __init alloc_event_buffer(struct amd_iommu *iommu)
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{
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	iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
						  get_order(EVT_BUFFER_SIZE));
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	return iommu->evt_buf ? 0 : -ENOMEM;
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}

static void iommu_enable_event_buffer(struct amd_iommu *iommu)
{
	u64 entry;

	BUG_ON(iommu->evt_buf == NULL);

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	entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
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	memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
		    &entry, sizeof(entry));

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	/* set head and tail to zero manually */
	writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
	writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);

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	iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
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}

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/*
 * This function disables the event log buffer
 */
static void iommu_disable_event_buffer(struct amd_iommu *iommu)
{
	iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
}

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static void __init free_event_buffer(struct amd_iommu *iommu)
{
	free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
}

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/* allocates the memory where the IOMMU will log its events to */
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static int __init alloc_ppr_log(struct amd_iommu *iommu)
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{
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	iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
						  get_order(PPR_LOG_SIZE));
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	return iommu->ppr_log ? 0 : -ENOMEM;
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}

static void iommu_enable_ppr_log(struct amd_iommu *iommu)
{
	u64 entry;

	if (iommu->ppr_log == NULL)
		return;

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	entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
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	memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
		    &entry, sizeof(entry));

	/* set head and tail to zero manually */
	writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
	writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);

	iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
	iommu_feature_enable(iommu, CONTROL_PPR_EN);
}

static void __init free_ppr_log(struct amd_iommu *iommu)
{
	if (iommu->ppr_log == NULL)
		return;

	free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
}

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static void free_ga_log(struct amd_iommu *iommu)
{
#ifdef CONFIG_IRQ_REMAP
	if (iommu->ga_log)
		free_pages((unsigned long)iommu->ga_log,
			    get_order(GA_LOG_SIZE));
	if (iommu->ga_log_tail)
		free_pages((unsigned long)iommu->ga_log_tail,
			    get_order(8));
#endif
}

static int iommu_ga_log_enable(struct amd_iommu *iommu)
{
#ifdef CONFIG_IRQ_REMAP
	u32 status, i;

	if (!iommu->ga_log)
		return -EINVAL;

	status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);

	/* Check if already running */
	if (status & (MMIO_STATUS_GALOG_RUN_MASK))
		return 0;

	iommu_feature_enable(iommu, CONTROL_GAINT_EN);
	iommu_feature_enable(iommu, CONTROL_GALOG_EN);

	for (i = 0; i < LOOP_TIMEOUT; ++i) {
		status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
		if (status & (MMIO_STATUS_GALOG_RUN_MASK))
			break;
	}

	if (i >= LOOP_TIMEOUT)
		return -EINVAL;
#endif /* CONFIG_IRQ_REMAP */
	return 0;
}

#ifdef CONFIG_IRQ_REMAP
static int iommu_init_ga_log(struct amd_iommu *iommu)
{
	u64 entry;

	if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
		return 0;

	iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
					get_order(GA_LOG_SIZE));
	if (!iommu->ga_log)
		goto err_out;

	iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
					get_order(8));
	if (!iommu->ga_log_tail)
		goto err_out;

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	entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
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	memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
		    &entry, sizeof(entry));
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	entry = (iommu_virt_to_phys(iommu->ga_log_tail) &
		 (BIT_ULL(52)-1)) & ~7ULL;
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	memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
		    &entry, sizeof(entry));
	writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
	writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);

	return 0;
err_out:
	free_ga_log(iommu);
	return -EINVAL;
}
#endif /* CONFIG_IRQ_REMAP */

static int iommu_init_ga(struct amd_iommu *iommu)
{
	int ret = 0;

#ifdef CONFIG_IRQ_REMAP
	/* Note: We have already checked GASup from IVRS table.
	 *       Now, we need to make sure that GAMSup is set.
	 */
	if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
	    !iommu_feature(iommu, FEATURE_GAM_VAPIC))
		amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;

	ret = iommu_init_ga_log(iommu);
#endif /* CONFIG_IRQ_REMAP */

	return ret;
}

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static void iommu_enable_xt(struct amd_iommu *iommu)
{
#ifdef CONFIG_IRQ_REMAP
	/*
	 * XT mode (32-bit APIC destination ID) requires
	 * GA mode (128-bit IRTE support) as a prerequisite.
	 */
	if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) &&
	    amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
		iommu_feature_enable(iommu, CONTROL_XT_EN);
#endif /* CONFIG_IRQ_REMAP */
}

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static void iommu_enable_gt(struct amd_iommu *iommu)
{
	if (!iommu_feature(iommu, FEATURE_GT))
		return;

	iommu_feature_enable(iommu, CONTROL_GT_EN);
}

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/* sets a specific bit in the device table entry. */
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static void set_dev_entry_bit(u16 devid, u8 bit)
{
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	int i = (bit >> 6) & 0x03;
	int _bit = bit & 0x3f;
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	amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
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}

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static int get_dev_entry_bit(u16 devid, u8 bit)
{
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	int i = (bit >> 6) & 0x03;
	int _bit = bit & 0x3f;
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	return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
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}


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static bool copy_device_table(void)
{
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	u64 int_ctl, int_tab_len, entry = 0, last_entry = 0;
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	struct dev_table_entry *old_devtb = NULL;
	u32 lo, hi, devid, old_devtb_size;
	phys_addr_t old_devtb_phys;
	struct amd_iommu *iommu;
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	u16 dom_id, dte_v, irq_v;
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	gfp_t gfp_flag;
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	u64 tmp;
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	if (!amd_iommu_pre_enabled)
		return false;
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	pr_warn("Translation is already enabled - trying to copy translation structures\n");
	for_each_iommu(iommu) {
		/* All IOMMUs should use the same device table with the same size */
		lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET);
		hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);
		entry = (((u64) hi) << 32) + lo;
		if (last_entry && last_entry != entry) {
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			pr_err("IOMMU:%d should use the same dev table as others!\n",
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				iommu->index);
			return false;
		}
		last_entry = entry;

		old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12;
		if (old_devtb_size != dev_table_size) {
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			pr_err("The device table size of IOMMU:%d is not expected!\n",
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				iommu->index);
			return false;
		}
	}

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	/*
	 * When SME is enabled in the first kernel, the entry includes the
	 * memory encryption mask(sme_me_mask), we must remove the memory
	 * encryption mask to obtain the true physical address in kdump kernel.
	 */
	old_devtb_phys = __sme_clr(entry) & PAGE_MASK;

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	if (old_devtb_phys >= 0x100000000ULL) {
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		pr_err("The address of old device table is above 4G, not trustworthy!\n");
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		return false;
	}
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	old_devtb = (sme_active() && is_kdump_kernel())
		    ? (__force void *)ioremap_encrypted(old_devtb_phys,
							dev_table_size)
		    : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB);

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	if (!old_devtb)
		return false;

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	gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32;
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	old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag,
				get_order(dev_table_size));
	if (old_dev_tbl_cpy == NULL) {
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		pr_err("Failed to allocate memory for copying old device table!\n");
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		return false;
	}

	for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
		old_dev_tbl_cpy[devid] = old_devtb[devid];
		dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK;
		dte_v = old_devtb[devid].data[0] & DTE_FLAG_V;
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		if (dte_v && dom_id) {
			old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0];
			old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1];
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			__set_bit(dom_id, amd_iommu_pd_alloc_bitmap);
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			/* If gcr3 table existed, mask it out */
			if (old_devtb[devid].data[0] & DTE_FLAG_GV) {
				tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
				tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
				old_dev_tbl_cpy[devid].data[1] &= ~tmp;
				tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A;
				tmp |= DTE_FLAG_GV;
				old_dev_tbl_cpy[devid].data[0] &= ~tmp;
			}
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		}

		irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE;
		int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK;
		int_tab_len = old_devtb[devid].data[2] & DTE_IRQ_TABLE_LEN_MASK;
		if (irq_v && (int_ctl || int_tab_len)) {
			if ((int_ctl != DTE_IRQ_REMAP_INTCTL) ||
			    (int_tab_len != DTE_IRQ_TABLE_LEN)) {
				pr_err("Wrong old irq remapping flag: %#x\n", devid);
				return false;
			}

		        old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2];
		}
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	}
	memunmap(old_devtb);

	return true;
}

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void amd_iommu_apply_erratum_63(u16 devid)
{
	int sysmgt;

	sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
		 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);

	if (sysmgt == 0x01)
		set_dev_entry_bit(devid, DEV_ENTRY_IW);
}

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/* Writes the specific IOMMU for a device into the rlookup table */
static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
{
	amd_iommu_rlookup_table[devid] = iommu;
}

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/*
 * This function takes the device specific flags read from the ACPI
 * table and sets up the device table entry with that information
 */
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static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
					   u16 devid, u32 flags, u32 ext_flags)
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{
	if (flags & ACPI_DEVFLAG_INITPASS)
		set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
	if (flags & ACPI_DEVFLAG_EXTINT)
		set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
	if (flags & ACPI_DEVFLAG_NMI)
		set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
	if (flags & ACPI_DEVFLAG_SYSMGT1)
		set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
	if (flags & ACPI_DEVFLAG_SYSMGT2)
		set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
	if (flags & ACPI_DEVFLAG_LINT0)
		set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
	if (flags & ACPI_DEVFLAG_LINT1)
		set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);

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	amd_iommu_apply_erratum_63(devid);

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	set_iommu_for_device(iommu, devid);
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}

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int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
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{
	struct devid_map *entry;
	struct list_head *list;

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	if (type == IVHD_SPECIAL_IOAPIC)
		list = &ioapic_map;
	else if (type == IVHD_SPECIAL_HPET)
		list = &hpet_map;
	else
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		return -EINVAL;

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	list_for_each_entry(entry, list, list) {
		if (!(entry->id == id && entry->cmd_line))
			continue;

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		pr_info("Command-line override present for %s id %d - ignoring\n",
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			type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);

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		*devid = entry->devid;

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		return 0;
	}

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	entry = kzalloc(sizeof(*entry), GFP_KERNEL);
	if (!entry)
		return -ENOMEM;

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	entry->id	= id;
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	entry->devid	= *devid;
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	entry->cmd_line	= cmd_line;
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	list_add_tail(&entry->list, list);

	return 0;
}

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static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
				      bool cmd_line)
{
	struct acpihid_map_entry *entry;
	struct list_head *list = &acpihid_map;

	list_for_each_entry(entry, list, list) {
		if (strcmp(entry->hid, hid) ||
		    (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
		    !entry->cmd_line)
			continue;

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		pr_info("Command-line override for hid:%s uid:%s\n",
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			hid, uid);
		*devid = entry->devid;
		return 0;
	}

	entry = kzalloc(sizeof(*entry), GFP_KERNEL);
	if (!entry)
		return -ENOMEM;

	memcpy(entry->uid, uid, strlen(uid));
	memcpy(entry->hid, hid, strlen(hid));
	entry->devid = *devid;
	entry->cmd_line	= cmd_line;
	entry->root_devid = (entry->devid & (~0x7));

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	pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n",
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		entry->cmd_line ? "cmd" : "ivrs",
		entry->hid, entry->uid, entry->root_devid);

	list_add_tail(&entry->list, list);
	return 0;
}

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static int __init add_early_maps(void)
{
	int i, ret;

	for (i = 0; i < early_ioapic_map_size; ++i) {
		ret = add_special_device(IVHD_SPECIAL_IOAPIC,
					 early_ioapic_map[i].id,
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					 &early_ioapic_map[i].devid,
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					 early_ioapic_map[i].cmd_line);
		if (ret)
			return ret;
	}

	for (i = 0; i < early_hpet_map_size; ++i) {
		ret = add_special_device(IVHD_SPECIAL_HPET,
					 early_hpet_map[i].id,
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					 &early_hpet_map[i].devid,
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					 early_hpet_map[i].cmd_line);
		if (ret)
			return ret;
	}

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	for (i = 0; i < early_acpihid_map_size; ++i) {
		ret = add_acpi_hid_device(early_acpihid_map[i].hid,
					  early_acpihid_map[i].uid,
					  &early_acpihid_map[i].devid,
					  early_acpihid_map[i].cmd_line);
		if (ret)
			return ret;
	}

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	return 0;
}

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/*
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 * Reads the device exclusion range from ACPI and initializes the IOMMU with
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 * it
 */
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static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
{
	struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];

	if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
		return;

	if (iommu) {
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		/*
		 * We only can configure exclusion ranges per IOMMU, not
		 * per device. But we can enable the exclusion range per
		 * device. This is done here
		 */
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		set_dev_entry_bit(devid, DEV_ENTRY_EX);
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		iommu->exclusion_start = m->range_start;
		iommu->exclusion_length = m->range_length;
	}
}

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/*
 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
 * initializes the hardware and our data structures with it.
 */
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static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
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					struct ivhd_header *h)
{
	u8 *p = (u8 *)h;
	u8 *end = p, flags = 0;
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	u16 devid = 0, devid_start = 0, devid_to = 0;
	u32 dev_i, ext_flags = 0;
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	bool alias = false;
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	struct ivhd_entry *e;
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	u32 ivhd_size;
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	int ret;


	ret = add_early_maps();
	if (ret)
		return ret;
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	amd_iommu_apply_ivrs_quirks();

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	/*
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	 * First save the recommended feature enable bits from ACPI
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	 */
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	iommu->acpi_flags = h->flags;
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	/*
	 * Done. Now parse the device entries
	 */
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	ivhd_size = get_ivhd_header_size(h);
	if (!ivhd_size) {
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		pr_err("Unsupported IVHD type %#x\n", h->type);
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		return -EINVAL;
	}

	p += ivhd_size;

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	end += h->length;

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	while (p < end) {
		e = (struct ivhd_entry *)p;
		switch (e->type) {
		case IVHD_DEV_ALL:
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			DUMP_printk("  DEV_ALL\t\t\tflags: %02x\n", e->flags);
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			for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
				set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
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			break;
		case IVHD_DEV_SELECT:
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			DUMP_printk("  DEV_SELECT\t\t\t devid: %02x:%02x.%x "
				    "flags: %02x\n",
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				    PCI_BUS_NUM(e->devid),
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				    PCI_SLOT(e->devid),
				    PCI_FUNC(e->devid),
				    e->flags);

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			devid = e->devid;
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			set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
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			break;
		case IVHD_DEV_SELECT_RANGE_START:
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			DUMP_printk("  DEV_SELECT_RANGE_START\t "
				    "devid: %02x:%02x.%x flags: %02x\n",
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				    PCI_BUS_NUM(e->devid),
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				    PCI_SLOT(e->devid),
				    PCI_FUNC(e->devid),
				    e->flags);

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