regmap-irq.c 21.8 KB
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/*
 * regmap based irq_chip
 *
 * Copyright 2011 Wolfson Microelectronics plc
 *
 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

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#include <linux/device.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>

#include "internal.h"

struct regmap_irq_chip_data {
	struct mutex lock;
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	struct irq_chip irq_chip;
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	struct regmap *map;
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	const struct regmap_irq_chip *chip;
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	int irq_base;
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	struct irq_domain *domain;
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	int irq;
	int wake_count;

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	void *status_reg_buf;
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	unsigned int *status_buf;
	unsigned int *mask_buf;
	unsigned int *mask_buf_def;
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	unsigned int *wake_buf;
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	unsigned int *type_buf;
	unsigned int *type_buf_def;
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	unsigned int irq_reg_stride;
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	unsigned int type_reg_stride;
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};

static inline const
struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
				     int irq)
{
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	return &data->chip->irqs[irq];
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}

static void regmap_irq_lock(struct irq_data *data)
{
	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);

	mutex_lock(&d->lock);
}

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static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
				  unsigned int reg, unsigned int mask,
				  unsigned int val)
{
	if (d->chip->mask_writeonly)
		return regmap_write_bits(d->map, reg, mask, val);
	else
		return regmap_update_bits(d->map, reg, mask, val);
}

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static void regmap_irq_sync_unlock(struct irq_data *data)
{
	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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	struct regmap *map = d->map;
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	int i, ret;
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	u32 reg;
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	u32 unmask_offset;
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	if (d->chip->runtime_pm) {
		ret = pm_runtime_get_sync(map->dev);
		if (ret < 0)
			dev_err(map->dev, "IRQ sync failed to resume: %d\n",
				ret);
	}

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	/*
	 * If there's been a change in the mask write it back to the
	 * hardware.  We rely on the use of the regmap core cache to
	 * suppress pointless writes.
	 */
	for (i = 0; i < d->chip->num_regs; i++) {
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		reg = d->chip->mask_base +
			(i * map->reg_stride * d->irq_reg_stride);
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		if (d->chip->mask_invert) {
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			ret = regmap_irq_update_bits(d, reg,
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					 d->mask_buf_def[i], ~d->mask_buf[i]);
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		} else if (d->chip->unmask_base) {
			/* set mask with mask_base register */
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			ret = regmap_irq_update_bits(d, reg,
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					d->mask_buf_def[i], ~d->mask_buf[i]);
			if (ret < 0)
				dev_err(d->map->dev,
					"Failed to sync unmasks in %x\n",
					reg);
			unmask_offset = d->chip->unmask_base -
							d->chip->mask_base;
			/* clear mask with unmask_base register */
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			ret = regmap_irq_update_bits(d,
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					reg + unmask_offset,
					d->mask_buf_def[i],
					d->mask_buf[i]);
		} else {
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			ret = regmap_irq_update_bits(d, reg,
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					 d->mask_buf_def[i], d->mask_buf[i]);
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		}
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		if (ret != 0)
			dev_err(d->map->dev, "Failed to sync masks in %x\n",
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				reg);
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		reg = d->chip->wake_base +
			(i * map->reg_stride * d->irq_reg_stride);
		if (d->wake_buf) {
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			if (d->chip->wake_invert)
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				ret = regmap_irq_update_bits(d, reg,
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							 d->mask_buf_def[i],
							 ~d->wake_buf[i]);
			else
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				ret = regmap_irq_update_bits(d, reg,
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							 d->mask_buf_def[i],
							 d->wake_buf[i]);
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			if (ret != 0)
				dev_err(d->map->dev,
					"Failed to sync wakes in %x: %d\n",
					reg, ret);
		}
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		if (!d->chip->init_ack_masked)
			continue;
		/*
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		 * Ack all the masked interrupts unconditionally,
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		 * OR if there is masked interrupt which hasn't been Acked,
		 * it'll be ignored in irq handler, then may introduce irq storm
		 */
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		if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
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			reg = d->chip->ack_base +
				(i * map->reg_stride * d->irq_reg_stride);
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			/* some chips ack by write 0 */
			if (d->chip->ack_invert)
				ret = regmap_write(map, reg, ~d->mask_buf[i]);
			else
				ret = regmap_write(map, reg, d->mask_buf[i]);
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			if (ret != 0)
				dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
					reg, ret);
		}
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	}

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	/* Don't update the type bits if we're using mask bits for irq type. */
	if (!d->chip->type_in_mask) {
		for (i = 0; i < d->chip->num_type_reg; i++) {
			if (!d->type_buf_def[i])
				continue;
			reg = d->chip->type_base +
				(i * map->reg_stride * d->type_reg_stride);
			if (d->chip->type_invert)
				ret = regmap_irq_update_bits(d, reg,
					d->type_buf_def[i], ~d->type_buf[i]);
			else
				ret = regmap_irq_update_bits(d, reg,
					d->type_buf_def[i], d->type_buf[i]);
			if (ret != 0)
				dev_err(d->map->dev, "Failed to sync type in %x\n",
					reg);
		}
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	}

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	if (d->chip->runtime_pm)
		pm_runtime_put(map->dev);

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	/* If we've changed our wakeup count propagate it to the parent */
	if (d->wake_count < 0)
		for (i = d->wake_count; i < 0; i++)
			irq_set_irq_wake(d->irq, 0);
	else if (d->wake_count > 0)
		for (i = 0; i < d->wake_count; i++)
			irq_set_irq_wake(d->irq, 1);

	d->wake_count = 0;

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	mutex_unlock(&d->lock);
}

static void regmap_irq_enable(struct irq_data *data)
{
	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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	struct regmap *map = d->map;
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	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
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	unsigned int mask, type;

	type = irq_data->type_falling_mask | irq_data->type_rising_mask;

	/*
	 * The type_in_mask flag means that the underlying hardware uses
	 * separate mask bits for rising and falling edge interrupts, but
	 * we want to make them into a single virtual interrupt with
	 * configurable edge.
	 *
	 * If the interrupt we're enabling defines the falling or rising
	 * masks then instead of using the regular mask bits for this
	 * interrupt, use the value previously written to the type buffer
	 * at the corresponding offset in regmap_irq_set_type().
	 */
	if (d->chip->type_in_mask && type)
		mask = d->type_buf[irq_data->reg_offset / map->reg_stride];
	else
		mask = irq_data->mask;
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	d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask;
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}

static void regmap_irq_disable(struct irq_data *data)
{
	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
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	struct regmap *map = d->map;
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	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
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	d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
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}

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static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
{
	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
	struct regmap *map = d->map;
	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
	int reg = irq_data->type_reg_offset / map->reg_stride;

	if (!(irq_data->type_rising_mask | irq_data->type_falling_mask))
		return 0;

	d->type_buf[reg] &= ~(irq_data->type_falling_mask |
					irq_data->type_rising_mask);
	switch (type) {
	case IRQ_TYPE_EDGE_FALLING:
		d->type_buf[reg] |= irq_data->type_falling_mask;
		break;

	case IRQ_TYPE_EDGE_RISING:
		d->type_buf[reg] |= irq_data->type_rising_mask;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		d->type_buf[reg] |= (irq_data->type_falling_mask |
					irq_data->type_rising_mask);
		break;

	default:
		return -EINVAL;
	}
	return 0;
}

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static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
{
	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
	struct regmap *map = d->map;
	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);

	if (on) {
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		if (d->wake_buf)
			d->wake_buf[irq_data->reg_offset / map->reg_stride]
				&= ~irq_data->mask;
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		d->wake_count++;
	} else {
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		if (d->wake_buf)
			d->wake_buf[irq_data->reg_offset / map->reg_stride]
				|= irq_data->mask;
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		d->wake_count--;
	}

	return 0;
}

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static const struct irq_chip regmap_irq_chip = {
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	.irq_bus_lock		= regmap_irq_lock,
	.irq_bus_sync_unlock	= regmap_irq_sync_unlock,
	.irq_disable		= regmap_irq_disable,
	.irq_enable		= regmap_irq_enable,
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	.irq_set_type		= regmap_irq_set_type,
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	.irq_set_wake		= regmap_irq_set_wake,
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};

static irqreturn_t regmap_irq_thread(int irq, void *d)
{
	struct regmap_irq_chip_data *data = d;
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	const struct regmap_irq_chip *chip = data->chip;
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	struct regmap *map = data->map;
	int ret, i;
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	bool handled = false;
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	u32 reg;
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	if (chip->handle_pre_irq)
		chip->handle_pre_irq(chip->irq_drv_data);

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	if (chip->runtime_pm) {
		ret = pm_runtime_get_sync(map->dev);
		if (ret < 0) {
			dev_err(map->dev, "IRQ thread failed to resume: %d\n",
				ret);
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			pm_runtime_put(map->dev);
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			goto exit;
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		}
	}

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	/*
	 * Read in the statuses, using a single bulk read if possible
	 * in order to reduce the I/O overheads.
	 */
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	if (!map->use_single_read && map->reg_stride == 1 &&
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	    data->irq_reg_stride == 1) {
		u8 *buf8 = data->status_reg_buf;
		u16 *buf16 = data->status_reg_buf;
		u32 *buf32 = data->status_reg_buf;
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		BUG_ON(!data->status_reg_buf);

		ret = regmap_bulk_read(map, chip->status_base,
				       data->status_reg_buf,
				       chip->num_regs);
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		if (ret != 0) {
			dev_err(map->dev, "Failed to read IRQ status: %d\n",
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				ret);
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			goto exit;
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		}
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		for (i = 0; i < data->chip->num_regs; i++) {
			switch (map->format.val_bytes) {
			case 1:
				data->status_buf[i] = buf8[i];
				break;
			case 2:
				data->status_buf[i] = buf16[i];
				break;
			case 4:
				data->status_buf[i] = buf32[i];
				break;
			default:
				BUG();
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				goto exit;
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			}
		}

	} else {
		for (i = 0; i < data->chip->num_regs; i++) {
			ret = regmap_read(map, chip->status_base +
					  (i * map->reg_stride
					   * data->irq_reg_stride),
					  &data->status_buf[i]);

			if (ret != 0) {
				dev_err(map->dev,
					"Failed to read IRQ status: %d\n",
					ret);
				if (chip->runtime_pm)
					pm_runtime_put(map->dev);
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				goto exit;
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			}
		}
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	}
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	/*
	 * Ignore masked IRQs and ack if we need to; we ack early so
	 * there is no race between handling and acknowleding the
	 * interrupt.  We assume that typically few of the interrupts
	 * will fire simultaneously so don't worry about overhead from
	 * doing a write per register.
	 */
	for (i = 0; i < data->chip->num_regs; i++) {
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		data->status_buf[i] &= ~data->mask_buf[i];

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		if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
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			reg = chip->ack_base +
				(i * map->reg_stride * data->irq_reg_stride);
			ret = regmap_write(map, reg, data->status_buf[i]);
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			if (ret != 0)
				dev_err(map->dev, "Failed to ack 0x%x: %d\n",
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					reg, ret);
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		}
	}

	for (i = 0; i < chip->num_irqs; i++) {
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		if (data->status_buf[chip->irqs[i].reg_offset /
				     map->reg_stride] & chip->irqs[i].mask) {
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			handle_nested_irq(irq_find_mapping(data->domain, i));
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			handled = true;
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		}
	}

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	if (chip->runtime_pm)
		pm_runtime_put(map->dev);

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exit:
	if (chip->handle_post_irq)
		chip->handle_post_irq(chip->irq_drv_data);

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	if (handled)
		return IRQ_HANDLED;
	else
		return IRQ_NONE;
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}

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static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
			  irq_hw_number_t hw)
{
	struct regmap_irq_chip_data *data = h->host_data;

	irq_set_chip_data(virq, data);
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	irq_set_chip(virq, &data->irq_chip);
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	irq_set_nested_thread(virq, 1);
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	irq_set_parent(virq, data->irq);
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	irq_set_noprobe(virq);

	return 0;
}

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static const struct irq_domain_ops regmap_domain_ops = {
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	.map	= regmap_irq_map,
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	.xlate	= irq_domain_xlate_onetwocell,
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};

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/**
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 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
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 *
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 * @map: The regmap for the device.
 * @irq: The IRQ the device uses to signal interrupts.
 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 * @chip: Configuration for the interrupt controller.
 * @data: Runtime data structure for the controller, allocated on success.
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 *
 * Returns 0 on success or an errno on failure.
 *
 * In order for this to be efficient the chip really should use a
 * register cache.  The chip driver is responsible for restoring the
 * register values used by the IRQ controller over suspend and resume.
 */
int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
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			int irq_base, const struct regmap_irq_chip *chip,
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			struct regmap_irq_chip_data **data)
{
	struct regmap_irq_chip_data *d;
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	int i;
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	int ret = -ENOMEM;
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	int num_type_reg;
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	u32 reg;
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	u32 unmask_offset;
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	if (chip->num_regs <= 0)
		return -EINVAL;

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	for (i = 0; i < chip->num_irqs; i++) {
		if (chip->irqs[i].reg_offset % map->reg_stride)
			return -EINVAL;
		if (chip->irqs[i].reg_offset / map->reg_stride >=
		    chip->num_regs)
			return -EINVAL;
	}

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	if (irq_base) {
		irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
		if (irq_base < 0) {
			dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
				 irq_base);
			return irq_base;
		}
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	}

	d = kzalloc(sizeof(*d), GFP_KERNEL);
	if (!d)
		return -ENOMEM;

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	d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
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				GFP_KERNEL);
	if (!d->status_buf)
		goto err_alloc;

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	d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
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			      GFP_KERNEL);
	if (!d->mask_buf)
		goto err_alloc;

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	d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
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				  GFP_KERNEL);
	if (!d->mask_buf_def)
		goto err_alloc;

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	if (chip->wake_base) {
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		d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
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				      GFP_KERNEL);
		if (!d->wake_buf)
			goto err_alloc;
	}

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	num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg;
	if (num_type_reg) {
		d->type_buf_def = kcalloc(num_type_reg,
					  sizeof(unsigned int), GFP_KERNEL);
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		if (!d->type_buf_def)
			goto err_alloc;

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		d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int),
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				      GFP_KERNEL);
		if (!d->type_buf)
			goto err_alloc;
	}

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	d->irq_chip = regmap_irq_chip;
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	d->irq_chip.name = chip->name;
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	d->irq = irq;
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	d->map = map;
	d->chip = chip;
	d->irq_base = irq_base;
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	if (chip->irq_reg_stride)
		d->irq_reg_stride = chip->irq_reg_stride;
	else
		d->irq_reg_stride = 1;

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	if (chip->type_reg_stride)
		d->type_reg_stride = chip->type_reg_stride;
	else
		d->type_reg_stride = 1;

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	if (!map->use_single_read && map->reg_stride == 1 &&
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	    d->irq_reg_stride == 1) {
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		d->status_reg_buf = kmalloc_array(chip->num_regs,
						  map->format.val_bytes,
						  GFP_KERNEL);
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		if (!d->status_reg_buf)
			goto err_alloc;
	}

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	mutex_init(&d->lock);

	for (i = 0; i < chip->num_irqs; i++)
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		d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
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			|= chip->irqs[i].mask;

	/* Mask all the interrupts by default */
	for (i = 0; i < chip->num_regs; i++) {
		d->mask_buf[i] = d->mask_buf_def[i];
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		reg = chip->mask_base +
			(i * map->reg_stride * d->irq_reg_stride);
555
		if (chip->mask_invert)
556
			ret = regmap_irq_update_bits(d, reg,
557
					 d->mask_buf[i], ~d->mask_buf[i]);
558
559
560
		else if (d->chip->unmask_base) {
			unmask_offset = d->chip->unmask_base -
					d->chip->mask_base;
561
			ret = regmap_irq_update_bits(d,
562
563
564
565
					reg + unmask_offset,
					d->mask_buf[i],
					d->mask_buf[i]);
		} else
566
			ret = regmap_irq_update_bits(d, reg,
567
					 d->mask_buf[i], d->mask_buf[i]);
568
569
		if (ret != 0) {
			dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
570
				reg, ret);
571
572
			goto err_alloc;
		}
573
574
575
576
577
578
579
580
581
582
583
584
585
586

		if (!chip->init_ack_masked)
			continue;

		/* Ack masked but set interrupts */
		reg = chip->status_base +
			(i * map->reg_stride * d->irq_reg_stride);
		ret = regmap_read(map, reg, &d->status_buf[i]);
		if (ret != 0) {
			dev_err(map->dev, "Failed to read IRQ status: %d\n",
				ret);
			goto err_alloc;
		}

587
		if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
588
589
			reg = chip->ack_base +
				(i * map->reg_stride * d->irq_reg_stride);
590
591
592
593
594
			if (chip->ack_invert)
				ret = regmap_write(map, reg,
					~(d->status_buf[i] & d->mask_buf[i]));
			else
				ret = regmap_write(map, reg,
595
596
597
598
599
600
601
					d->status_buf[i] & d->mask_buf[i]);
			if (ret != 0) {
				dev_err(map->dev, "Failed to ack 0x%x: %d\n",
					reg, ret);
				goto err_alloc;
			}
		}
602
603
	}

604
605
606
607
608
609
	/* Wake is disabled by default */
	if (d->wake_buf) {
		for (i = 0; i < chip->num_regs; i++) {
			d->wake_buf[i] = d->mask_buf_def[i];
			reg = chip->wake_base +
				(i * map->reg_stride * d->irq_reg_stride);
610
611

			if (chip->wake_invert)
612
				ret = regmap_irq_update_bits(d, reg,
613
614
615
							 d->mask_buf_def[i],
							 0);
			else
616
				ret = regmap_irq_update_bits(d, reg,
617
618
							 d->mask_buf_def[i],
							 d->wake_buf[i]);
619
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623
624
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626
			if (ret != 0) {
				dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
					reg, ret);
				goto err_alloc;
			}
		}
	}

627
	if (chip->num_type_reg && !chip->type_in_mask) {
628
629
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633
		for (i = 0; i < chip->num_type_reg; ++i) {
			if (!d->type_buf_def[i])
				continue;

			reg = chip->type_base +
				(i * map->reg_stride * d->type_reg_stride);
634
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636
637
638
639
640
641

			ret = regmap_read(map, reg, &d->type_buf_def[i]);

			if (d->chip->type_invert)
				d->type_buf_def[i] = ~d->type_buf_def[i];

			if (ret) {
				dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n",
642
643
644
645
646
647
					reg, ret);
				goto err_alloc;
			}
		}
	}

648
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652
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656
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658
659
	if (irq_base)
		d->domain = irq_domain_add_legacy(map->dev->of_node,
						  chip->num_irqs, irq_base, 0,
						  &regmap_domain_ops, d);
	else
		d->domain = irq_domain_add_linear(map->dev->of_node,
						  chip->num_irqs,
						  &regmap_domain_ops, d);
	if (!d->domain) {
		dev_err(map->dev, "Failed to create IRQ domain\n");
		ret = -ENOMEM;
		goto err_alloc;
660
661
	}

662
663
	ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
				   irq_flags | IRQF_ONESHOT,
664
665
				   chip->name, d);
	if (ret != 0) {
666
667
		dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
			irq, chip->name, ret);
668
		goto err_domain;
669
670
	}

671
672
	*data = d;

673
674
	return 0;

675
676
err_domain:
	/* Should really dispose of the domain but... */
677
err_alloc:
678
679
	kfree(d->type_buf);
	kfree(d->type_buf_def);
680
	kfree(d->wake_buf);
681
682
683
	kfree(d->mask_buf_def);
	kfree(d->mask_buf);
	kfree(d->status_buf);
684
	kfree(d->status_reg_buf);
685
686
687
688
689
690
	kfree(d);
	return ret;
}
EXPORT_SYMBOL_GPL(regmap_add_irq_chip);

/**
691
 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
692
693
 *
 * @irq: Primary IRQ for the device
694
 * @d: &regmap_irq_chip_data allocated by regmap_add_irq_chip()
695
 *
696
 * This function also disposes of all mapped IRQs on the chip.
697
698
699
 */
void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
{
700
701
702
	unsigned int virq;
	int hwirq;

703
704
705
706
	if (!d)
		return;

	free_irq(irq, d);
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722

	/* Dispose all virtual irq from irq domain before removing it */
	for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
		/* Ignore hwirq if holes in the IRQ list */
		if (!d->chip->irqs[hwirq].mask)
			continue;

		/*
		 * Find the virtual irq of hwirq on chip and if it is
		 * there then dispose it
		 */
		virq = irq_find_mapping(d->domain, hwirq);
		if (virq)
			irq_dispose_mapping(virq);
	}

723
	irq_domain_remove(d->domain);
724
725
	kfree(d->type_buf);
	kfree(d->type_buf_def);
726
	kfree(d->wake_buf);
727
728
	kfree(d->mask_buf_def);
	kfree(d->mask_buf);
729
	kfree(d->status_reg_buf);
730
731
732
733
	kfree(d->status_buf);
	kfree(d);
}
EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
734

735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
static void devm_regmap_irq_chip_release(struct device *dev, void *res)
{
	struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;

	regmap_del_irq_chip(d->irq, d);
}

static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)

{
	struct regmap_irq_chip_data **r = res;

	if (!r || !*r) {
		WARN_ON(!r || !*r);
		return 0;
	}
	return *r == data;
}

/**
755
 * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
756
 *
757
758
759
 * @dev: The device pointer on which irq_chip belongs to.
 * @map: The regmap for the device.
 * @irq: The IRQ the device uses to signal interrupts
760
 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
761
762
763
 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 * @chip: Configuration for the interrupt controller.
 * @data: Runtime data structure for the controller, allocated on success
764
765
766
 *
 * Returns 0 on success or an errno on failure.
 *
767
 * The &regmap_irq_chip_data will be automatically released when the device is
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
 * unbound.
 */
int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
			     int irq_flags, int irq_base,
			     const struct regmap_irq_chip *chip,
			     struct regmap_irq_chip_data **data)
{
	struct regmap_irq_chip_data **ptr, *d;
	int ret;

	ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
			   GFP_KERNEL);
	if (!ptr)
		return -ENOMEM;

	ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base,
				  chip, &d);
	if (ret < 0) {
		devres_free(ptr);
		return ret;
	}

	*ptr = d;
	devres_add(dev, ptr);
	*data = d;
	return 0;
}
EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);

/**
798
 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
799
800
 *
 * @dev: Device for which which resource was allocated.
801
802
803
804
 * @irq: Primary IRQ for the device.
 * @data: &regmap_irq_chip_data allocated by regmap_add_irq_chip().
 *
 * A resource managed version of regmap_del_irq_chip().
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
 */
void devm_regmap_del_irq_chip(struct device *dev, int irq,
			      struct regmap_irq_chip_data *data)
{
	int rc;

	WARN_ON(irq != data->irq);
	rc = devres_release(dev, devm_regmap_irq_chip_release,
			    devm_regmap_irq_chip_match, data);

	if (rc != 0)
		WARN_ON(rc);
}
EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);

820
/**
821
 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
822
 *
823
 * @data: regmap irq controller to operate on.
824
 *
825
 * Useful for drivers to request their own IRQs.
826
827
828
 */
int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
{
829
	WARN_ON(!data->irq_base);
830
831
832
	return data->irq_base;
}
EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
833
834

/**
835
 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
836
 *
837
838
 * @data: regmap irq controller to operate on.
 * @irq: index of the interrupt requested in the chip IRQs.
839
 *
840
 * Useful for drivers to request their own IRQs.
841
842
843
 */
int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
{
844
845
846
847
	/* Handle holes in the IRQ list */
	if (!data->chip->irqs[irq].mask)
		return -EINVAL;

848
849
850
	return irq_create_mapping(data->domain, irq);
}
EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
851
852

/**
853
854
855
 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
 *
 * @data: regmap_irq controller to operate on.
856
857
858
859
860
861
862
863
864
865
866
867
868
869
 *
 * Useful for drivers to request their own IRQs and for integration
 * with subsystems.  For ease of integration NULL is accepted as a
 * domain, allowing devices to just call this even if no domain is
 * allocated.
 */
struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
{
	if (data)
		return data->domain;
	else
		return NULL;
}
EXPORT_SYMBOL_GPL(regmap_irq_get_domain);