spi-ath79.c 6.14 KB
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// SPDX-License-Identifier: GPL-2.0-only
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/*
 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
 *
 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 *
 * This driver has been based on the spi-gpio.c:
 *	Copyright (C) 2006,2008 David Brownell
 */

#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/bitops.h>
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#include <linux/clk.h>
#include <linux/err.h>
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#include <linux/platform_data/spi-ath79.h>
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#define DRV_NAME	"ath79-spi"

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#define ATH79_SPI_RRW_DELAY_FACTOR	12000
#define MHZ				(1000 * 1000)

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#define AR71XX_SPI_REG_FS		0x00	/* Function Select */
#define AR71XX_SPI_REG_CTRL		0x04	/* SPI Control */
#define AR71XX_SPI_REG_IOC		0x08	/* SPI I/O Control */
#define AR71XX_SPI_REG_RDS		0x0c	/* Read Data Shift */

#define AR71XX_SPI_FS_GPIO		BIT(0)	/* Enable GPIO mode */

#define AR71XX_SPI_IOC_DO		BIT(0)	/* Data Out pin */
#define AR71XX_SPI_IOC_CLK		BIT(8)	/* CLK pin */
#define AR71XX_SPI_IOC_CS(n)		BIT(16 + (n))

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struct ath79_spi {
	struct spi_bitbang	bitbang;
	u32			ioc_base;
	u32			reg_ctrl;
	void __iomem		*base;
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	struct clk		*clk;
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	unsigned int		rrw_delay;
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};

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static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
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{
	return ioread32(sp->base + reg);
}

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static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
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{
	iowrite32(val, sp->base + reg);
}

static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
{
	return spi_master_get_devdata(spi->master);
}

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static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
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{
	if (nsecs > sp->rrw_delay)
		ndelay(nsecs - sp->rrw_delay);
}

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static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
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	u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
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	if (cs_high)
		sp->ioc_base |= cs_bit;
	else
		sp->ioc_base &= ~cs_bit;
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	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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}

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static void ath79_spi_enable(struct ath79_spi *sp)
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{
	/* enable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);

	/* save CTRL register */
	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);

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	/* clear clk and mosi in the base state */
	sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);

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	/* TODO: setup speed? */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
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}

static void ath79_spi_disable(struct ath79_spi *sp)
{
	/* restore CTRL register */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	/* disable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
}

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static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
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			       u32 word, u8 bits, unsigned flags)
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{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	u32 ioc = sp->ioc_base;

	/* clock starts at inactive polarity */
	for (word <<= (32 - bits); likely(bits); bits--) {
		u32 out;

		if (word & (1 << 31))
			out = ioc | AR71XX_SPI_IOC_DO;
		else
			out = ioc & ~AR71XX_SPI_IOC_DO;

		/* setup MSB (to slave) on trailing edge */
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
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		ath79_spi_delay(sp, nsecs);
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		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
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		ath79_spi_delay(sp, nsecs);
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		if (bits == 1)
			ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
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		word <<= 1;
	}

	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
}

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static int ath79_spi_probe(struct platform_device *pdev)
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{
	struct spi_master *master;
	struct ath79_spi *sp;
	struct ath79_spi_platform_data *pdata;
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	unsigned long rate;
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	int ret;

	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	if (master == NULL) {
		dev_err(&pdev->dev, "failed to allocate spi master\n");
		return -ENOMEM;
	}

	sp = spi_master_get_devdata(master);
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	master->dev.of_node = pdev->dev.of_node;
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	platform_set_drvdata(pdev, sp);

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	pdata = dev_get_platdata(&pdev->dev);
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	master->use_gpio_descriptors = true;
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	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
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	master->setup = spi_bitbang_setup;
	master->cleanup = spi_bitbang_cleanup;
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	if (pdata) {
		master->bus_num = pdata->bus_num;
		master->num_chipselect = pdata->num_chipselect;
	}

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	sp->bitbang.master = master;
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	sp->bitbang.chipselect = ath79_spi_chipselect;
	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
	sp->bitbang.flags = SPI_CS_HIGH;

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	sp->base = devm_platform_ioremap_resource(pdev, 0);
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	if (IS_ERR(sp->base)) {
		ret = PTR_ERR(sp->base);
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		goto err_put_master;
	}

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	sp->clk = devm_clk_get(&pdev->dev, "ahb");
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	if (IS_ERR(sp->clk)) {
		ret = PTR_ERR(sp->clk);
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		goto err_put_master;
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	}

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	ret = clk_prepare_enable(sp->clk);
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	if (ret)
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		goto err_put_master;
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	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	if (!rate) {
		ret = -EINVAL;
		goto err_clk_disable;
	}

	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
		sp->rrw_delay);

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	ath79_spi_enable(sp);
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	ret = spi_bitbang_start(&sp->bitbang);
	if (ret)
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		goto err_disable;
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	return 0;

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err_disable:
	ath79_spi_disable(sp);
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err_clk_disable:
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	clk_disable_unprepare(sp->clk);
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err_put_master:
	spi_master_put(sp->bitbang.master);

	return ret;
}

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static int ath79_spi_remove(struct platform_device *pdev)
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{
	struct ath79_spi *sp = platform_get_drvdata(pdev);

	spi_bitbang_stop(&sp->bitbang);
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	ath79_spi_disable(sp);
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	clk_disable_unprepare(sp->clk);
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	spi_master_put(sp->bitbang.master);

	return 0;
}

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static void ath79_spi_shutdown(struct platform_device *pdev)
{
	ath79_spi_remove(pdev);
}

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static const struct of_device_id ath79_spi_of_match[] = {
	{ .compatible = "qca,ar7100-spi", },
	{ },
};
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MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
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static struct platform_driver ath79_spi_driver = {
	.probe		= ath79_spi_probe,
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	.remove		= ath79_spi_remove,
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	.shutdown	= ath79_spi_shutdown,
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	.driver		= {
		.name	= DRV_NAME,
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		.of_match_table = ath79_spi_of_match,
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	},
};
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module_platform_driver(ath79_spi_driver);
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MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);