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  • Max Filippov's avatar
    xtensa: fix TLBTEMP_BASE_2 region handling in fast_second_level_miss · 7128039f
    Max Filippov authored
    
    
    Current definition of TLBTEMP_BASE_2 is always 32K above the
    TLBTEMP_BASE_1, whereas fast_second_level_miss handler for the TLBTEMP
    region analyzes virtual address bit (PAGE_SHIFT + DCACHE_ALIAS_ORDER)
    to determine TLBTEMP region where the fault happened. The size of the
    TLBTEMP region is also checked incorrectly: not 64K, but twice data
    cache way size (whicht may as well be less than the instruction cache
    way size).
    
    Fix TLBTEMP_BASE_2 to be TLBTEMP_BASE_1 + data cache way size.
    Provide TLBTEMP_SIZE that is a greater of doubled data cache way size or
    the instruction cache way size, and use it to determine if the second
    level TLB miss occured in the TLBTEMP region.
    
    Practical occurence of page faults in the TLBTEMP area is extremely
    rare, this code can be tested by deletion of all w[di]tlb instructions
    in the tlbtemp_mapping region.
    
    Cc: stable@vger.kernel.org
    Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    7128039f