Commit 29c4dfd9 authored by Chris Zankel's avatar Chris Zankel
Browse files

[XTENSA] Remove non-rt signal handling



The non-rt signal handling was never really used, so we don't break
anything. This patch also cleans up the signal stack-frame to make
it independent from the processor configuration. It also improves
the method used for controlling single-stepping. We now save and
restore the 'icountlevel' register that controls single stepping
and set or clear the saved state to enable or disable it.

Signed-off-by: default avatarChris Zankel <chris@zankel.net>
parent adba09f0
......@@ -39,6 +39,7 @@ int main(void)
DEFINE(PT_LEND, offsetof (struct pt_regs, lend));
DEFINE(PT_LCOUNT, offsetof (struct pt_regs, lcount));
DEFINE(PT_SAR, offsetof (struct pt_regs, sar));
DEFINE(PT_ICOUNTLEVEL, offsetof (struct pt_regs, icountlevel));
DEFINE(PT_SYSCALL, offsetof (struct pt_regs, syscall));
DEFINE(PT_AREG, offsetof (struct pt_regs, areg[0]));
DEFINE(PT_AREG0, offsetof (struct pt_regs, areg[0]));
......
......@@ -125,8 +125,9 @@ _user_exception:
movi a2, 0
rsr a3, SAR
wsr a2, ICOUNTLEVEL
xsr a2, ICOUNTLEVEL
s32i a3, a1, PT_SAR
s32i a2, a1, PT_ICOUNTLEVEL
/* Rotate ws so that the current windowbase is at bit0. */
/* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
......@@ -276,8 +277,9 @@ _kernel_exception:
movi a2, 0
rsr a3, SAR
wsr a2, ICOUNTLEVEL
xsr a2, ICOUNTLEVEL
s32i a3, a1, PT_SAR
s32i a2, a1, PT_ICOUNTLEVEL
/* Rotate ws so that the current windowbase is at bit0. */
/* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
......@@ -330,14 +332,16 @@ _kernel_exception:
common_exception:
/* Save EXCVADDR, DEBUGCAUSE, and PC, and clear LCOUNT */
/* Save some registers, disable loops and clear the syscall flag. */
rsr a2, DEBUGCAUSE
rsr a3, EPC_1
s32i a2, a1, PT_DEBUGCAUSE
s32i a3, a1, PT_PC
movi a2, -1
rsr a3, EXCVADDR
s32i a2, a1, PT_SYSCALL
movi a2, 0
s32i a3, a1, PT_EXCVADDR
xsr a2, LCOUNT
......@@ -450,27 +454,8 @@ common_exception_return:
/* Restore the state of the task and return from the exception. */
/* If we are returning from a user exception, and the process
* to run next has PT_SINGLESTEP set, we want to setup
* ICOUNT and ICOUNTLEVEL to step one instruction.
* PT_SINGLESTEP is set by sys_ptrace (ptrace.c)
*/
4: /* a2 holds GET_CURRENT(a2,a1) */
l32i a3, a2, TI_TASK
l32i a3, a3, TASK_PTRACE
bbci.l a3, PT_SINGLESTEP_BIT, 1f # jump if single-step flag is not set
movi a3, -2 # PT_SINGLESTEP flag is set,
movi a4, 1 # icountlevel of 1 means it won't
wsr a3, ICOUNT # start counting until after rfe
wsr a4, ICOUNTLEVEL # so setup icount & icountlevel.
isync
1:
#if XCHAL_EXTRA_SA_SIZE
/* For user exceptions, restore the extra state from the user's TCB. */
......@@ -665,6 +650,13 @@ common_exception_exit:
wsr a3, LEND
wsr a2, LCOUNT
/* We control single stepping through the ICOUNTLEVEL register. */
l32i a2, a1, PT_ICOUNTLEVEL
movi a3, -2
wsr a2, ICOUNTLEVEL
wsr a3, ICOUNT
/* Check if it was double exception. */
l32i a0, a1, PT_DEPC
......
This diff is collapsed.
......@@ -64,6 +64,7 @@ typedef struct {
# define COPROCESSOR_INFO_SIZE 8
# endif
#endif
#endif /* XCHAL_HAVE_CP */
#ifndef __ASSEMBLY__
......@@ -74,8 +75,11 @@ extern void save_coprocessor_registers(void*, int);
# else
# define release_coprocessors(task)
# endif
#endif
#endif
typedef unsigned char cp_state_t[XTENSA_CP_EXTRA_SIZE]
__attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN)));
#endif /* !__ASSEMBLY__ */
#endif /* _XTENSA_COPROCESSOR_H */
......@@ -13,7 +13,6 @@
#ifndef _XTENSA_ELF_H
#define _XTENSA_ELF_H
#include <asm/variant/core.h>
#include <asm/ptrace.h>
/* Xtensa processor ELF architecture-magic number */
......@@ -49,7 +48,7 @@ typedef struct {
elf_greg_t lcount;
elf_greg_t sar;
elf_greg_t syscall;
elf_greg_t ar[XCHAL_NUM_AREGS];
elf_greg_t ar[64];
} xtensa_gregset_t;
#define ELF_NGREG (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t))
......
......@@ -99,7 +99,8 @@ struct pt_regs {
unsigned long windowbase; /* 48 */
unsigned long windowstart; /* 52 */
unsigned long syscall; /* 56 */
int reserved[2]; /* 64 */
unsigned long icountlevel; /* 60 */
int reserved[1]; /* 64 */
/* Make sure the areg field is 16 bytes aligned. */
int align[0] __attribute__ ((aligned(16)));
......
......@@ -5,21 +5,12 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 - 2003 Tensilica Inc.
* Copyright (C) 2001 - 2007 Tensilica Inc.
*/
#ifndef _XTENSA_SIGCONTEXT_H
#define _XTENSA_SIGCONTEXT_H
#define _ASMLANGUAGE
#include <asm/processor.h>
#include <asm/coprocessor.h>
struct _cpstate {
unsigned char _cpstate[XTENSA_CP_EXTRA_SIZE];
} __attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN)));
struct sigcontext {
unsigned long oldmask;
......@@ -27,18 +18,13 @@ struct sigcontext {
/* CPU registers */
unsigned long sc_pc;
unsigned long sc_ps;
unsigned long sc_wmask;
unsigned long sc_windowbase;
unsigned long sc_windowstart;
unsigned long sc_lbeg;
unsigned long sc_lend;
unsigned long sc_lcount;
unsigned long sc_sar;
unsigned long sc_depc;
unsigned long sc_dareg0;
unsigned long sc_treg[4];
unsigned long sc_areg[XCHAL_NUM_AREGS];
struct _cpstate *sc_cpstate;
unsigned long sc_acclo;
unsigned long sc_acchi;
unsigned long sc_a[16];
};
#endif /* __ASM_XTENSA_SIGCONTEXT_H */
#endif /* _XTENSA_SIGCONTEXT_H */
......@@ -485,8 +485,8 @@ __SYSCALL(217, sys_sched_get_priority_min, 1)
__SYSCALL(218, sys_sched_rr_get_interval, 2)
#define __NR_sched_yield 219
__SYSCALL(219, sys_sched_yield, 0)
#define __NR_sigreturn 222
__SYSCALL(222, xtensa_sigreturn, 0)
#define __NR_available222 222
__SYSCALL(222, sys_ni_syscall, 0)
/* Signal Handling */
......
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