Verified Commit 91d0c59f authored by Tomer Maimon's avatar Tomer Maimon Committed by Mark Brown
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dt-binding: spi: add NPCM FIU controller

Added device tree binding documentation for Nuvoton BMC
NPCM Flash Interface Unit(FIU) SPI master controller
using SPI-MEM interface.

Signed-off-by: default avatarTomer Maimon <>

Signed-off-by: Mark Brown's avatarMark Brown <>
parent 3bd158c5
* Nuvoton FLASH Interface Unit (FIU) SPI Controller
NPCM FIU supports single, dual and quad communication interface.
The NPCM7XX supports three FIU modules,
FIU0 and FIUx supports two chip selects,
FIU3 support four chip select.
Required properties:
- compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
- #address-cells : should be 1.
- #size-cells : should be 0.
- reg : the first contains the register location and length,
the second contains the memory mapping address and length
- reg-names: Should contain the reg names "control" and "memory"
- clocks : phandle of FIU reference clock.
Required properties in case the pins can be muxed:
- pinctrl-names : a pinctrl state named "default" must be defined.
- pinctrl-0 : phandle referencing pin configuration of the device.
Optional property:
- nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
- All the FIU controller nodes should be represented in the aliases node using
the following format 'fiu{n}' where n is a unique number for the alias.
fiu0 represent fiu 0 controller
fiu1 represent fiu 3 controller
fiu2 represent fiu x controller
fiu3: spi@c00000000 {
compatible = "nuvoton,npcm750-fiu";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
reg-names = "control", "memory";
clocks = <&clk NPCM7XX_CLK_AHB>;
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins>;
spi-nor@0 {
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