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linux-arm
linux-vs
Commits
b769c5ba
Verified
Commit
b769c5ba
authored
Sep 15, 2019
by
Mark Brown
Browse files
Merge branch 'spi-5.4' into spi-next
parents
262a2f33
fdeae8f5
Changes
74
Expand all
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Inline
Side-by-side
Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
0 → 100644
View file @
b769c5ba
* Nuvoton FLASH Interface Unit (FIU) SPI Controller
NPCM FIU supports single, dual and quad communication interface.
The NPCM7XX supports three FIU modules,
FIU0 and FIUx supports two chip selects,
FIU3 support four chip select.
Required properties:
- compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
- #address-cells : should be 1.
- #size-cells : should be 0.
- reg : the first contains the register location and length,
the second contains the memory mapping address and length
- reg-names: Should contain the reg names "control" and "memory"
- clocks : phandle of FIU reference clock.
Required properties in case the pins can be muxed:
- pinctrl-names : a pinctrl state named "default" must be defined.
- pinctrl-0 : phandle referencing pin configuration of the device.
Optional property:
- nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
Aliases:
- All the FIU controller nodes should be represented in the aliases node using
the following format 'fiu{n}' where n is a unique number for the alias.
In the NPCM7XX BMC:
fiu0 represent fiu 0 controller
fiu1 represent fiu 3 controller
fiu2 represent fiu x controller
Example:
fiu3: spi@c00000000 {
compatible = "nuvoton,npcm750-fiu";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
reg-names = "control", "memory";
clocks = <&clk NPCM7XX_CLK_AHB>;
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins>;
spi-nor@0 {
...
};
};
Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
View file @
b769c5ba
...
...
@@ -3,9 +3,8 @@
Required properties:
- compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
"fsl,imx7d-qspi", "fsl,imx6ul-qspi",
"fsl,ls1021a-qspi"
"fsl,ls1021a-qspi"
, "fsl,ls2080a-qspi"
or
"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
- reg : the first contains the register location and length,
the second contains the memory mapping address and length
...
...
@@ -34,7 +33,11 @@ qspi0: quadspi@40044000 {
clock-names = "qspi_en", "qspi";
flash0: s25fl128s@0 {
....
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl128s", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
...
...
Documentation/devicetree/bindings/spi/spi-mt65xx.txt
View file @
b769c5ba
...
...
@@ -5,6 +5,7 @@ Required properties:
- mediatek,mt2701-spi: for mt2701 platforms
- mediatek,mt2712-spi: for mt2712 platforms
- mediatek,mt6589-spi: for mt6589 platforms
- mediatek,mt6765-spi: for mt6765 platforms
- mediatek,mt7622-spi: for mt7622 platforms
- "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
- mediatek,mt8135-spi: for mt8135 platforms
...
...
Documentation/devicetree/bindings/spi/spi-sprd-adi.txt
View file @
b769c5ba
...
...
@@ -25,18 +25,23 @@ data by ADI software channels at the same time, or two parallel routine of setti
ADI registers will make ADI controller registers chaos to lead incorrect results.
Then we need one hardware spinlock to synchronize between the multiple subsystems.
The new version ADI controller supplies multiple master channels for different
subsystem accessing, that means no need to add hardware spinlock to synchronize,
thus change the hardware spinlock support to be optional to keep backward
compatibility.
Required properties:
- compatible: Should be "sprd,sc9860-adi".
- reg: Offset and length of ADI-SPI controller register space.
- hwlocks: Reference to a phandle of a hwlock provider node.
- hwlock-names: Reference to hwlock name strings defined in the same order
as the hwlocks, should be "adi".
- #address-cells: Number of cells required to define a chip select address
on the ADI-SPI bus. Should be set to 1.
- #size-cells: Size of cells required to define a chip select address size
on the ADI-SPI bus. Should be set to 0.
Optional properties:
- hwlocks: Reference to a phandle of a hwlock provider node.
- hwlock-names: Reference to hwlock name strings defined in the same order
as the hwlocks, should be "adi".
- sprd,hw-channels: This is an array of channel values up to 49 channels.
The first value specifies the hardware channel id which is used to
transfer data triggered by hardware automatically, and the second
...
...
arch/arm/mach-ep93xx/edb93xx.c
View file @
b769c5ba
...
...
@@ -103,7 +103,7 @@ static struct spi_board_info edb93xx_spi_board_info[] __initdata = {
};
static
struct
gpiod_lookup_table
edb93xx_spi_cs_gpio_table
=
{
.
dev_id
=
"
ep93xx-
spi
.
0"
,
.
dev_id
=
"spi0"
,
.
table
=
{
GPIO_LOOKUP
(
"A"
,
6
,
"cs"
,
GPIO_ACTIVE_LOW
),
{
},
...
...
arch/arm/mach-ep93xx/simone.c
View file @
b769c5ba
...
...
@@ -73,7 +73,7 @@ static struct spi_board_info simone_spi_devices[] __initdata = {
* v1.3 parts will still work, since the signal on SFRMOUT is automatic.
*/
static
struct
gpiod_lookup_table
simone_spi_cs_gpio_table
=
{
.
dev_id
=
"
ep93xx-
spi
.
0"
,
.
dev_id
=
"spi0"
,
.
table
=
{
GPIO_LOOKUP
(
"A"
,
1
,
"cs"
,
GPIO_ACTIVE_LOW
),
{
},
...
...
arch/arm/mach-ep93xx/ts72xx.c
View file @
b769c5ba
...
...
@@ -267,7 +267,7 @@ static struct spi_board_info bk3_spi_board_info[] __initdata = {
* goes through CPLD
*/
static
struct
gpiod_lookup_table
bk3_spi_cs_gpio_table
=
{
.
dev_id
=
"
ep93xx-
spi
.
0"
,
.
dev_id
=
"spi0"
,
.
table
=
{
GPIO_LOOKUP
(
"F"
,
3
,
"cs"
,
GPIO_ACTIVE_LOW
),
{
},
...
...
@@ -316,7 +316,7 @@ static struct spi_board_info ts72xx_spi_devices[] __initdata = {
};
static
struct
gpiod_lookup_table
ts72xx_spi_cs_gpio_table
=
{
.
dev_id
=
"
ep93xx-
spi
.
0"
,
.
dev_id
=
"spi0"
,
.
table
=
{
/* DIO_17 */
GPIO_LOOKUP
(
"F"
,
2
,
"cs"
,
GPIO_ACTIVE_LOW
),
...
...
arch/arm/mach-ep93xx/vision_ep9307.c
View file @
b769c5ba
...
...
@@ -242,7 +242,7 @@ static struct spi_board_info vision_spi_board_info[] __initdata = {
};
static
struct
gpiod_lookup_table
vision_spi_cs_gpio_table
=
{
.
dev_id
=
"
ep93xx-
spi
.
0"
,
.
dev_id
=
"spi0"
,
.
table
=
{
GPIO_LOOKUP_IDX
(
"A"
,
6
,
"cs"
,
0
,
GPIO_ACTIVE_LOW
),
GPIO_LOOKUP_IDX
(
"A"
,
7
,
"cs"
,
1
,
GPIO_ACTIVE_LOW
),
...
...
drivers/dma/bcm2835-dma.c
View file @
b769c5ba
...
...
@@ -37,10 +37,19 @@
#define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14
#define BCM2835_DMA_CHAN_NAME_SIZE 8
/**
* struct bcm2835_dmadev - BCM2835 DMA controller
* @ddev: DMA device
* @base: base address of register map
* @dma_parms: DMA parameters (to convey 1 GByte max segment size to clients)
* @zero_page: bus address of zero page (to detect transactions copying from
* zero page and avoid accessing memory if so)
*/
struct
bcm2835_dmadev
{
struct
dma_device
ddev
;
void
__iomem
*
base
;
struct
device_dma_parameters
dma_parms
;
dma_addr_t
zero_page
;
};
struct
bcm2835_dma_cb
{
...
...
@@ -687,11 +696,12 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
size_t
period_len
,
enum
dma_transfer_direction
direction
,
unsigned
long
flags
)
{
struct
bcm2835_dmadev
*
od
=
to_bcm2835_dma_dev
(
chan
->
device
);
struct
bcm2835_chan
*
c
=
to_bcm2835_dma_chan
(
chan
);
struct
bcm2835_desc
*
d
;
dma_addr_t
src
,
dst
;
u32
info
=
BCM2835_DMA_WAIT_RESP
;
u32
extra
=
BCM2835_DMA_INT_EN
;
u32
extra
=
0
;
size_t
max_len
=
bcm2835_dma_max_frame_length
(
c
);
size_t
frames
;
...
...
@@ -707,6 +717,11 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
return
NULL
;
}
if
(
flags
&
DMA_PREP_INTERRUPT
)
extra
|=
BCM2835_DMA_INT_EN
;
else
period_len
=
buf_len
;
/*
* warn if buf_len is not a multiple of period_len - this may leed
* to unexpected latencies for interrupts and thus audiable clicks
...
...
@@ -732,6 +747,10 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
dst
=
c
->
cfg
.
dst_addr
;
src
=
buf_addr
;
info
|=
BCM2835_DMA_D_DREQ
|
BCM2835_DMA_S_INC
;
/* non-lite channels can write zeroes w/o accessing memory */
if
(
buf_addr
==
od
->
zero_page
&&
!
c
->
is_lite_channel
)
info
|=
BCM2835_DMA_S_IGNORE
;
}
/* calculate number of frames */
...
...
@@ -778,7 +797,10 @@ static int bcm2835_dma_terminate_all(struct dma_chan *chan)
/* stop DMA activity */
if
(
c
->
desc
)
{
vchan_terminate_vdesc
(
&
c
->
desc
->
vd
);
if
(
c
->
desc
->
vd
.
tx
.
flags
&
DMA_PREP_INTERRUPT
)
vchan_terminate_vdesc
(
&
c
->
desc
->
vd
);
else
vchan_vdesc_fini
(
&
c
->
desc
->
vd
);
c
->
desc
=
NULL
;
bcm2835_dma_abort
(
c
);
}
...
...
@@ -831,6 +853,9 @@ static void bcm2835_dma_free(struct bcm2835_dmadev *od)
list_del
(
&
c
->
vc
.
chan
.
device_node
);
tasklet_kill
(
&
c
->
vc
.
task
);
}
dma_unmap_page_attrs
(
od
->
ddev
.
dev
,
od
->
zero_page
,
PAGE_SIZE
,
DMA_TO_DEVICE
,
DMA_ATTR_SKIP_CPU_SYNC
);
}
static
const
struct
of_device_id
bcm2835_dma_of_match
[]
=
{
...
...
@@ -907,11 +932,20 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
od
->
ddev
.
directions
=
BIT
(
DMA_DEV_TO_MEM
)
|
BIT
(
DMA_MEM_TO_DEV
)
|
BIT
(
DMA_MEM_TO_MEM
);
od
->
ddev
.
residue_granularity
=
DMA_RESIDUE_GRANULARITY_BURST
;
od
->
ddev
.
descriptor_reuse
=
true
;
od
->
ddev
.
dev
=
&
pdev
->
dev
;
INIT_LIST_HEAD
(
&
od
->
ddev
.
channels
);
platform_set_drvdata
(
pdev
,
od
);
od
->
zero_page
=
dma_map_page_attrs
(
od
->
ddev
.
dev
,
ZERO_PAGE
(
0
),
0
,
PAGE_SIZE
,
DMA_TO_DEVICE
,
DMA_ATTR_SKIP_CPU_SYNC
);
if
(
dma_mapping_error
(
od
->
ddev
.
dev
,
od
->
zero_page
))
{
dev_err
(
&
pdev
->
dev
,
"Failed to map zero page
\n
"
);
return
-
ENOMEM
;
}
/* Request DMA channel mask from device tree */
if
(
of_property_read_u32
(
pdev
->
dev
.
of_node
,
"brcm,dma-channel-mask"
,
...
...
drivers/platform/chrome/cros_ec_spi.c
View file @
b769c5ba
...
...
@@ -706,7 +706,7 @@ static int cros_ec_spi_devm_high_pri_alloc(struct device *dev,
struct
cros_ec_spi
*
ec_spi
)
{
struct
sched_param
sched_priority
=
{
.
sched_priority
=
MAX_RT_PRIO
-
1
,
.
sched_priority
=
MAX_RT_PRIO
/
2
,
};
int
err
;
...
...
drivers/spi/Kconfig
View file @
b769c5ba
...
...
@@ -433,6 +433,16 @@ config SPI_MT7621
help
This selects a driver for the MediaTek MT7621 SPI Controller.
config SPI_NPCM_FIU
tristate "Nuvoton NPCM FLASH Interface Unit"
depends on ARCH_NPCM || COMPILE_TEST
depends on OF && HAS_IOMEM
help
This enables support for the Flash Interface Unit SPI controller
in master mode.
This driver does not support generic SPI. The implementation only
supports spi-mem interface.
config SPI_NPCM_PSPI
tristate "Nuvoton NPCM PSPI Controller"
depends on ARCH_NPCM || COMPILE_TEST
...
...
drivers/spi/Makefile
View file @
b769c5ba
...
...
@@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
obj-$(CONFIG_SPI_MT7621)
+=
spi-mt7621.o
obj-$(CONFIG_SPI_MXIC)
+=
spi-mxic.o
obj-$(CONFIG_SPI_MXS)
+=
spi-mxs.o
obj-$(CONFIG_SPI_NPCM_FIU)
+=
spi-npcm-fiu.o
obj-$(CONFIG_SPI_NPCM_PSPI)
+=
spi-npcm-pspi.o
obj-$(CONFIG_SPI_NUC900)
+=
spi-nuc900.o
obj-$(CONFIG_SPI_NXP_FLEXSPI)
+=
spi-nxp-fspi.o
...
...
drivers/spi/atmel-quadspi.c
View file @
b769c5ba
...
...
@@ -526,7 +526,6 @@ static int atmel_qspi_probe(struct platform_device *pdev)
/* Request the IRQ */
irq
=
platform_get_irq
(
pdev
,
0
);
if
(
irq
<
0
)
{
dev_err
(
&
pdev
->
dev
,
"missing IRQ
\n
"
);
err
=
irq
;
goto
disable_qspick
;
}
...
...
drivers/spi/spi-altera.c
View file @
b769c5ba
...
...
@@ -170,7 +170,6 @@ static int altera_spi_probe(struct platform_device *pdev)
{
struct
altera_spi
*
hw
;
struct
spi_master
*
master
;
struct
resource
*
res
;
int
err
=
-
ENODEV
;
master
=
spi_alloc_master
(
&
pdev
->
dev
,
sizeof
(
struct
altera_spi
));
...
...
@@ -189,8 +188,7 @@ static int altera_spi_probe(struct platform_device *pdev)
hw
=
spi_master_get_devdata
(
master
);
/* find and map our resources */
res
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
hw
->
base
=
devm_ioremap_resource
(
&
pdev
->
dev
,
res
);
hw
->
base
=
devm_platform_ioremap_resource
(
pdev
,
0
);
if
(
IS_ERR
(
hw
->
base
))
{
err
=
PTR_ERR
(
hw
->
base
);
goto
exit
;
...
...
drivers/spi/spi-armada-3700.c
View file @
b769c5ba
...
...
@@ -817,7 +817,6 @@ static int a3700_spi_probe(struct platform_device *pdev)
{
struct
device
*
dev
=
&
pdev
->
dev
;
struct
device_node
*
of_node
=
dev
->
of_node
;
struct
resource
*
res
;
struct
spi_master
*
master
;
struct
a3700_spi
*
spi
;
u32
num_cs
=
0
;
...
...
@@ -855,8 +854,7 @@ static int a3700_spi_probe(struct platform_device *pdev)
spi
->
master
=
master
;
res
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
spi
->
base
=
devm_ioremap_resource
(
dev
,
res
);
spi
->
base
=
devm_platform_ioremap_resource
(
pdev
,
0
);
if
(
IS_ERR
(
spi
->
base
))
{
ret
=
PTR_ERR
(
spi
->
base
);
goto
error
;
...
...
@@ -864,7 +862,6 @@ static int a3700_spi_probe(struct platform_device *pdev)
irq
=
platform_get_irq
(
pdev
,
0
);
if
(
irq
<
0
)
{
dev_err
(
dev
,
"could not get irq: %d
\n
"
,
irq
);
ret
=
-
ENXIO
;
goto
error
;
}
...
...
drivers/spi/spi-ath79.c
View file @
b769c5ba
...
...
@@ -139,7 +139,6 @@ static int ath79_spi_probe(struct platform_device *pdev)
struct
spi_master
*
master
;
struct
ath79_spi
*
sp
;
struct
ath79_spi_platform_data
*
pdata
;
struct
resource
*
r
;
unsigned
long
rate
;
int
ret
;
...
...
@@ -169,8 +168,7 @@ static int ath79_spi_probe(struct platform_device *pdev)
sp
->
bitbang
.
txrx_word
[
SPI_MODE_0
]
=
ath79_spi_txrx_mode0
;
sp
->
bitbang
.
flags
=
SPI_CS_HIGH
;
r
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
sp
->
base
=
devm_ioremap_resource
(
&
pdev
->
dev
,
r
);
sp
->
base
=
devm_platform_ioremap_resource
(
pdev
,
0
);
if
(
IS_ERR
(
sp
->
base
))
{
ret
=
PTR_ERR
(
sp
->
base
);
goto
err_put_master
;
...
...
drivers/spi/spi-atmel.c
View file @
b769c5ba
...
...
@@ -23,6 +23,7 @@
#include
<linux/gpio/consumer.h>
#include
<linux/pinctrl/consumer.h>
#include
<linux/pm_runtime.h>
#include
<trace/events/spi.h>
/* SPI register offsets */
#define SPI_CR 0x0000
...
...
@@ -1409,9 +1410,13 @@ static int atmel_spi_transfer_one_message(struct spi_master *master,
msg
->
actual_length
=
0
;
list_for_each_entry
(
xfer
,
&
msg
->
transfers
,
transfer_list
)
{
trace_spi_transfer_start
(
msg
,
xfer
);
ret
=
atmel_spi_one_transfer
(
master
,
msg
,
xfer
);
if
(
ret
)
goto
msg_done
;
trace_spi_transfer_stop
(
msg
,
xfer
);
}
if
(
as
->
use_pdc
)
...
...
drivers/spi/spi-axi-spi-engine.c
View file @
b769c5ba
...
...
@@ -460,7 +460,6 @@ static int spi_engine_probe(struct platform_device *pdev)
struct
spi_engine
*
spi_engine
;
struct
spi_master
*
master
;
unsigned
int
version
;
struct
resource
*
res
;
int
irq
;
int
ret
;
...
...
@@ -480,8 +479,7 @@ static int spi_engine_probe(struct platform_device *pdev)
spin_lock_init
(
&
spi_engine
->
lock
);
res
=
platform_get_resource
(
pdev
,
IORESOURCE_MEM
,
0
);
spi_engine
->
base
=
devm_ioremap_resource
(
&
pdev
->
dev
,
res
);
spi_engine
->
base
=
devm_platform_ioremap_resource
(
pdev
,
0
);
if
(
IS_ERR
(
spi_engine
->
base
))
{
ret
=
PTR_ERR
(
spi_engine
->
base
);
goto
err_put_master
;
...
...
drivers/spi/spi-bcm-qspi.c
View file @
b769c5ba
...
...
@@ -897,6 +897,7 @@ static int bcm_qspi_transfer_one(struct spi_master *master,
read_from_hw
(
qspi
,
slots
);
}
bcm_qspi_enable_bspi
(
qspi
);
return
0
;
}
...
...
drivers/spi/spi-bcm2835.c
View file @
b769c5ba
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