Commit ea982ba7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC updates from Ulf Hansson:
 "MMC core:
   - Fixup processing of SDIO IRQs during system suspend/resume
   - Add helper function to indicate if SDIO IRQs is enabled

  MMC host:
   - bcm2835: Take SWIOTLB memory size limitation into account
   - dw_mmc: Improve SDIO IRQs support
   - mtk-sd: Various improvements
   - mtk-sd: Improve SDIO IRQs support
   - sdhci-iproc: Add support for emmc2 of the BCM2711
   - sdhci-of-arasan: Add Support for Intel LGM eMMC
   - sdhci-of-aspeed: Add support for the ASPEED SD controller
   - sdhci-of-esdhc: Deal with erratum A011334 support in ls1028a 1.0 SoC
   - sdhci-pci: Prepare to add support of Genesys Logic GL975x
   - sdhci-pci: Add another Id for Intel CML
   - sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issue
   - sunxi: Add support for H5 compatibles"

* tag 'mmc-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (59 commits)
  ms_block: fix spelling mistake "randomally" -> "randomly"
  mmc: dw_mmc: hi3798cv200: make array degrees static const, makes object smaller
  mmc: sdhci: Convert to use sdio_irq_claimed()
  mmc: sdhci: Drop redundant code for SDIO IRQs
  mmc: sdhci: Drop redundant check in sdhci_ack_sdio_irq()
  mmc: core: Fixup processing of SDIO IRQs during system suspend/resume
  mmc: core: WARN if SDIO IRQs are enabled for non-powered card in suspend
  mmc: core: Clarify that the ->ack_sdio_irq() callback is mandatory
  mmc: core: Clarify sdio_irq_pending flag for MMC_CAP2_SDIO_IRQ_NOTHREAD
  mmc: core: Move code to get pending SDIO IRQs to a function
  mmc: mtk-sd: Re-store SDIO IRQs mask at system resume
  mmc: dw_mmc: Re-store SDIO IRQs mask at system resume
  mmc: core: Add helper function to indicate if SDIO IRQs is enabled
  mmc: sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issue
  mmc: sdhci-pci-o2micro: Move functions in preparation to fix DLL lock phase shift issue
  mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name
  mmc: sdhci: Fix incorrect switch to HS mode
  mmc: sdhci-of-aspeed: Depend on CONFIG_OF_ADDRESS
  mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLK
  mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()
  ...
parents 7ad67ca5 b4611979
......@@ -30,16 +30,22 @@ properties:
- const: allwinner,sun8i-a83t-mmc
- const: allwinner,sun7i-a20-mmc
- items:
- const: allwinner,sun50i-h6-emmc
- const: allwinner,sun8i-r40-emmc
- const: allwinner,sun50i-a64-emmc
- items:
- const: allwinner,sun50i-h6-mmc
- const: allwinner,sun8i-r40-mmc
- const: allwinner,sun50i-a64-mmc
- items:
- const: allwinner,sun8i-r40-emmc
- const: allwinner,sun50i-h5-emmc
- const: allwinner,sun50i-a64-emmc
- items:
- const: allwinner,sun8i-r40-mmc
- const: allwinner,sun50i-h5-mmc
- const: allwinner,sun50i-a64-mmc
- items:
- const: allwinner,sun50i-h6-emmc
- const: allwinner,sun50i-a64-emmc
- items:
- const: allwinner,sun50i-h6-mmc
- const: allwinner,sun50i-a64-mmc
reg:
......
......@@ -17,6 +17,8 @@ Required Properties:
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
Note: This binding has been deprecated and moved to [5].
- "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
[5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
......@@ -80,3 +82,18 @@ Example:
phy-names = "phy_arasan";
#clock-cells = <0>;
};
emmc: sdhci@ec700000 {
compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
reg = <0xec700000 0x300>;
interrupt-parent = <&ioapic1>;
interrupts = <44 1>;
clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
<&cgu0 LGM_GCLK_EMMC>;
clock-names = "clk_xin", "clk_ahb", "gate";
clock-output-names = "emmc_cardclock";
#clock-cells = <0>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
arasan,soc-ctl-syscon = <&sysconf>;
};
# SPDX-License-Identifier: GPL-2.0-or-later
# Copyright 2019 IBM Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASPEED SD/SDIO/MMC Controller
maintainers:
- Andrew Jeffery <andrew@aj.id.au>
- Ryan Chen <ryanchen.aspeed@gmail.com>
description: |+
The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO
Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if
only a single slot is enabled.
The two slots are supported by a common configuration area. As the SDHCIs for
the slots are dependent on the common configuration area, they are described
as child nodes.
properties:
compatible:
enum:
- aspeed,ast2400-sd-controller
- aspeed,ast2500-sd-controller
- aspeed,ast2600-sd-controller
reg:
maxItems: 1
description: Common configuration registers
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
clocks:
maxItems: 1
description: The SD/SDIO controller clock gate
patternProperties:
"^sdhci@[0-9a-f]+$":
type: object
allOf:
- $ref: mmc-controller.yaml
properties:
compatible:
enum:
- aspeed,ast2400-sdhci
- aspeed,ast2500-sdhci
- aspeed,ast2600-sdhci
reg:
maxItems: 1
description: The SDHCI registers
clocks:
maxItems: 1
description: The SD bus clock
interrupts:
maxItems: 1
description: The SD interrupt shared between both slots
sdhci,auto-cmd12:
type: boolean
description: Specifies that controller should use auto CMD12
required:
- compatible
- reg
- clocks
- interrupts
additionalProperties: false
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
- clocks
examples:
- |
#include <dt-bindings/clock/aspeed-clock.h>
sdc@1e740000 {
compatible = "aspeed,ast2500-sd-controller";
reg = <0x1e740000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e740000 0x20000>;
clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
sdhci0: sdhci@100 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x100 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&syscon ASPEED_CLK_SDIO>;
};
sdhci1: sdhci@200 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x200 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&syscon ASPEED_CLK_SDIO>;
};
};
......@@ -6,10 +6,12 @@ by mmc.txt and the properties that represent the IPROC SDHCI controller.
Required properties:
- compatible : Should be one of the following
"brcm,bcm2835-sdhci"
"brcm,bcm2711-emmc2"
"brcm,sdhci-iproc-cygnus"
"brcm,sdhci-iproc"
Use brcm2835-sdhci for Rasperry PI.
Use brcm2835-sdhci for the eMMC controller on the BCM2835 (Raspberry Pi) and
bcm2711-emmc2 for the additional eMMC2 controller on BCM2711.
Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers
restricted to 32bit host accesses to SDHCI registers.
......
......@@ -1462,6 +1462,7 @@ F: arch/arm/mach-artpec
F: arch/arm/boot/dts/artpec6*
F: drivers/clk/axis
F: drivers/crypto/axis
F: drivers/mmc/host/usdhi6rol0.c
F: drivers/pinctrl/pinctrl-artpec*
F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
......
......@@ -1087,7 +1087,7 @@ static u16 msb_get_free_block(struct msb_data *msb, int zone)
pos %= msb->free_block_count[zone];
dbg_verbose("have %d choices for a free block, selected randomally: %d",
dbg_verbose("have %d choices for a free block, selected randomly: %d",
msb->free_block_count[zone], pos);
pba = find_next_zero_bit(msb->used_blocks_bitmap,
......
......@@ -847,8 +847,7 @@ static void r592_remove(struct pci_dev *pdev)
#ifdef CONFIG_PM_SLEEP
static int r592_suspend(struct device *core_dev)
{
struct pci_dev *pdev = to_pci_dev(core_dev);
struct r592_device *dev = pci_get_drvdata(pdev);
struct r592_device *dev = dev_get_drvdata(core_dev);
r592_clear_interrupts(dev);
memstick_suspend_host(dev->host);
......@@ -858,8 +857,7 @@ static int r592_suspend(struct device *core_dev)
static int r592_resume(struct device *core_dev)
{
struct pci_dev *pdev = to_pci_dev(core_dev);
struct r592_device *dev = pci_get_drvdata(pdev);
struct r592_device *dev = dev_get_drvdata(core_dev);
r592_clear_interrupts(dev);
r592_enable_device(dev, false);
......
......@@ -951,6 +951,8 @@ static int mmc_sdio_pre_suspend(struct mmc_host *host)
*/
static int mmc_sdio_suspend(struct mmc_host *host)
{
WARN_ON(host->sdio_irqs && !mmc_card_keep_power(host));
/* Prevent processing of SDIO IRQs in suspended state. */
mmc_card_set_suspended(host->card);
cancel_delayed_work_sync(&host->sdio_irq_work);
......@@ -1013,7 +1015,7 @@ static int mmc_sdio_resume(struct mmc_host *host)
if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD))
wake_up_process(host->sdio_irq_thread);
else if (host->caps & MMC_CAP_SDIO_IRQ)
host->ops->enable_sdio_irq(host, 1);
queue_delayed_work(system_wq, &host->sdio_irq_work, 0);
}
out:
......
......@@ -27,10 +27,39 @@
#include "core.h"
#include "card.h"
static int sdio_get_pending_irqs(struct mmc_host *host, u8 *pending)
{
struct mmc_card *card = host->card;
int ret;
WARN_ON(!host->claimed);
ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_INTx, 0, pending);
if (ret) {
pr_debug("%s: error %d reading SDIO_CCCR_INTx\n",
mmc_card_id(card), ret);
return ret;
}
if (*pending && mmc_card_broken_irq_polling(card) &&
!(host->caps & MMC_CAP_SDIO_IRQ)) {
unsigned char dummy;
/* A fake interrupt could be created when we poll SDIO_CCCR_INTx
* register with a Marvell SD8797 card. A dummy CMD52 read to
* function 0 register 0xff can avoid this.
*/
mmc_io_rw_direct(card, 0, 0, 0xff, 0, &dummy);
}
return 0;
}
static int process_sdio_pending_irqs(struct mmc_host *host)
{
struct mmc_card *card = host->card;
int i, ret, count;
bool sdio_irq_pending = host->sdio_irq_pending;
unsigned char pending;
struct sdio_func *func;
......@@ -38,34 +67,23 @@ static int process_sdio_pending_irqs(struct mmc_host *host)
if (mmc_card_suspended(card))
return 0;
/* Clear the flag to indicate that we have processed the IRQ. */
host->sdio_irq_pending = false;
/*
* Optimization, if there is only 1 function interrupt registered
* and we know an IRQ was signaled then call irq handler directly.
* Otherwise do the full probe.
*/
func = card->sdio_single_irq;
if (func && host->sdio_irq_pending) {
if (func && sdio_irq_pending) {
func->irq_handler(func);
return 1;
}
ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_INTx, 0, &pending);
if (ret) {
pr_debug("%s: error %d reading SDIO_CCCR_INTx\n",
mmc_card_id(card), ret);
ret = sdio_get_pending_irqs(host, &pending);
if (ret)
return ret;
}
if (pending && mmc_card_broken_irq_polling(card) &&
!(host->caps & MMC_CAP_SDIO_IRQ)) {
unsigned char dummy;
/* A fake interrupt could be created when we poll SDIO_CCCR_INTx
* register with a Marvell SD8797 card. A dummy CMD52 read to
* function 0 register 0xff can avoid this.
*/
mmc_io_rw_direct(card, 0, 0, 0xff, 0, &dummy);
}
count = 0;
for (i = 1; i <= 7; i++) {
......@@ -96,9 +114,8 @@ static void sdio_run_irqs(struct mmc_host *host)
{
mmc_claim_host(host);
if (host->sdio_irqs) {
host->sdio_irq_pending = true;
process_sdio_pending_irqs(host);
if (host->ops->ack_sdio_irq)
if (!host->sdio_irq_pending)
host->ops->ack_sdio_irq(host);
}
mmc_release_host(host);
......@@ -114,6 +131,7 @@ void sdio_irq_work(struct work_struct *work)
void sdio_signal_irq(struct mmc_host *host)
{
host->sdio_irq_pending = true;
queue_delayed_work(system_wq, &host->sdio_irq_work, 0);
}
EXPORT_SYMBOL_GPL(sdio_signal_irq);
......@@ -159,7 +177,6 @@ static int sdio_irq_thread(void *_host)
if (ret)
break;
ret = process_sdio_pending_irqs(host);
host->sdio_irq_pending = false;
mmc_release_host(host);
/*
......
......@@ -154,6 +154,18 @@ config MMC_SDHCI_OF_ARASAN
If unsure, say N.
config MMC_SDHCI_OF_ASPEED
tristate "SDHCI OF support for the ASPEED SDHCI controller"
depends on MMC_SDHCI_PLTFM
depends on OF && OF_ADDRESS
help
This selects the ASPEED Secure Digital Host Controller Interface.
If you have a controller with this interface, say Y or M here. You
also need to enable an appropriate bus interface.
If unsure, say N.
config MMC_SDHCI_OF_AT91
tristate "SDHCI OF support for the Atmel SDMMC controller"
depends on MMC_SDHCI_PLTFM
......
......@@ -84,6 +84,7 @@ obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o
obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o
obj-$(CONFIG_MMC_SDHCI_OF_ARASAN) += sdhci-of-arasan.o
obj-$(CONFIG_MMC_SDHCI_OF_ASPEED) += sdhci-of-aspeed.o
obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
......
......@@ -2413,6 +2413,7 @@ static void atmci_get_cap(struct atmel_mci *host)
case 0x600:
case 0x500:
host->caps.has_odd_clk_div = 1;
/* Fall through */
case 0x400:
case 0x300:
host->caps.has_dma_conf_reg = 1;
......@@ -2420,13 +2421,16 @@ static void atmci_get_cap(struct atmel_mci *host)
host->caps.has_cfg_reg = 1;
host->caps.has_cstor_reg = 1;
host->caps.has_highspeed = 1;
/* Fall through */
case 0x200:
host->caps.has_rwproof = 1;
host->caps.need_blksz_mul_4 = 0;
host->caps.need_notbusy_for_read_ops = 1;
/* Fall through */
case 0x100:
host->caps.has_bad_data_ordering = 0;
host->caps.need_reset_after_xfer = 0;
/* Fall through */
case 0x0:
break;
default:
......
......@@ -1314,7 +1314,7 @@ static int bcm2835_add_host(struct bcm2835_host *host)
}
mmc->max_segs = 128;
mmc->max_req_size = 524288;
mmc->max_req_size = min_t(size_t, 524288, dma_max_mapping_size(dev));
mmc->max_seg_size = mmc->max_req_size;
mmc->max_blk_size = 1024;
mmc->max_blk_count = 65535;
......@@ -1409,7 +1409,6 @@ static int bcm2835_probe(struct platform_device *pdev)
host->irq = platform_get_irq(pdev, 0);
if (host->irq <= 0) {
dev_err(dev, "get IRQ failed\n");
ret = -EINVAL;
goto err;
}
......
......@@ -66,7 +66,7 @@ static void dw_mci_hi3798cv200_set_ios(struct dw_mci *host, struct mmc_ios *ios)
static int dw_mci_hi3798cv200_execute_tuning(struct dw_mci_slot *slot,
u32 opcode)
{
int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 };
static const int degrees[] = { 0, 45, 90, 135, 180, 225, 270, 315 };
struct dw_mci *host = slot->host;
struct hi3798cv200_priv *priv = host->priv;
int raise_point = -1, fall_point = -1;
......
......@@ -3460,6 +3460,10 @@ int dw_mci_runtime_resume(struct device *dev)
/* Force setup bus to guarantee available clock output */
dw_mci_setup_bus(host->slot, true);
/* Re-enable SDIO interrupts. */
if (sdio_irq_claimed(host->slot->mmc))
__dw_mci_enable_sdio_irq(host->slot, 1);
/* Now that slots are all setup, we can enable card detect */
dw_mci_enable_cd(host);
......
......@@ -25,8 +25,6 @@
#include <asm/cacheflush.h>
#include <asm/mach-jz4740/dma.h>
#define JZ_REG_MMC_STRPCL 0x00
#define JZ_REG_MMC_STATUS 0x04
#define JZ_REG_MMC_CLKRT 0x08
......@@ -186,9 +184,9 @@ static void jz4740_mmc_write_irq_reg(struct jz4740_mmc_host *host,
uint32_t val)
{
if (host->version >= JZ_MMC_JZ4780)
return writel(val, host->base + JZ_REG_MMC_IREG);
writel(val, host->base + JZ_REG_MMC_IREG);
else
return writew(val, host->base + JZ_REG_MMC_IREG);
writew(val, host->base + JZ_REG_MMC_IREG);
}
static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host)
......@@ -292,11 +290,9 @@ static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host,
if (data->flags & MMC_DATA_WRITE) {
conf.direction = DMA_MEM_TO_DEV;
conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
conf.slave_id = JZ4740_DMA_TYPE_MMC_TRANSMIT;
} else {
conf.direction = DMA_DEV_TO_MEM;
conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
conf.slave_id = JZ4740_DMA_TYPE_MMC_RECEIVE;
}
sg_count = jz4740_mmc_prepare_dma_data(host, data, COOKIE_MAPPED);
......@@ -820,14 +816,14 @@ static irqreturn_t jz_mmc_irq(int irq, void *devid)
del_timer(&host->timeout_timer);
if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
cmd->error = -ETIMEDOUT;
cmd->error = -ETIMEDOUT;
} else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
cmd->error = -EIO;
cmd->error = -EIO;
} else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
if (cmd->data)
cmd->data->error = -EIO;
cmd->error = -EIO;
if (cmd->data)
cmd->data->error = -EIO;
cmd->error = -EIO;
}
jz4740_mmc_set_irq_enabled(host, irq_reg, false);
......@@ -969,7 +965,6 @@ static int jz4740_mmc_probe(struct platform_device* pdev)
host->irq = platform_get_irq(pdev, 0);
if (host->irq < 0) {
ret = host->irq;
dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
goto err_free_host;
}
......
......@@ -1091,7 +1091,6 @@ static int meson_mmc_probe(struct platform_device *pdev)
host->irq = platform_get_irq(pdev, 0);
if (host->irq <= 0) {
dev_err(&pdev->dev, "failed to get interrupt resource.\n");
ret = -EINVAL;
goto free_host;
}
......
......@@ -891,7 +891,7 @@ mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,
/* Handle scatterlist segments one at a time, with synch for
* each 512-byte block
*/
for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) {
for_each_sg(data->sg, sg, data->sg_len, n_sg) {
int status = 0;
dma_addr_t dma_addr = 0;
void *kmap_addr;
......
......@@ -1219,47 +1219,58 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
(MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
return;
/*
* ST Micro variant: handle busy detection.
*/
/* Handle busy detection on DAT0 if the variant supports it. */
if (busy_resp && host->variant->busy_detect) {
/* We are busy with a command, return */
if (host->busy_status &&
(status & host->variant->busy_detect_flag))
return;
/*
* We were not busy, but we now got a busy response on
* something that was not an error, and we double-check
* that the special busy status bit is still set before
* proceeding.
* Before unmasking for the busy end IRQ, confirm that the
* command was sent successfully. To keep track of having a
* command in-progress, waiting for busy signaling to end,
* store the status in host->busy_status.
*
* Note that, the card may need a couple of clock cycles before
* it starts signaling busy on DAT0, hence re-read the
* MMCISTATUS register here, to allow the busy bit to be set.
* Potentially we may even need to poll the register for a
* while, to allow it to be set, but tests indicates that it
* isn't needed.
*/
if (!host->busy_status &&
!(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
(readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
/* Clear the busy start IRQ */
writel(host->variant->busy_detect_mask,
host->base + MMCICLEAR);
/* Unmask the busy end IRQ */
writel(readl(base + MMCIMASK0) |
host->variant->busy_detect_mask,
base + MMCIMASK0);
/*
* Now cache the last response status code (until
* the busy bit goes low), and return.
*/
host->busy_status =
status & (MCI_CMDSENT|MCI_CMDRESPEND);
return;
}
/*
* At this point we are not busy with a command, we have
* not received a new busy request, clear and mask the busy
* end IRQ and fall through to process the IRQ.
* If there is a command in-progress that has been successfully
* sent, then bail out if busy status is set and wait for the
* busy end IRQ.
*
* Note that, the HW triggers an IRQ on both edges while
* monitoring DAT0 for busy completion, but there is only one
* status bit in MMCISTATUS for the busy state. Therefore
* both the start and the end interrupts needs to be cleared,
* one after the other. So, clear the busy start IRQ here.
*/
if (host->busy_status &&
(status & host->variant->busy_detect_flag)) {
writel(host->variant->busy_detect_mask,
host->base + MMCICLEAR);
return;
}
/*
* If there is a command in-progress that has been successfully
* sent and the busy bit isn't set, it means we have received
* the busy end IRQ. Clear and mask the IRQ, then continue to
* process the command.
*/
if (host->busy_status) {
......@@ -1505,14 +1516,8 @@ static irqreturn_t mmci_irq(int irq, void *dev_id)
}
/*
* We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's
* enabled) in mmci_cmd_irq() function where ST Micro busy
* detection variant is handled. Considering the HW seems to be
* triggering the IRQ on both edges while monitoring DAT0 for
* busy completion and that same status bit is used to monitor
* start and end of busy detection, special care must be taken