1. 22 Feb, 2019 1 commit
  2. 20 Feb, 2019 2 commits
  3. 19 Feb, 2019 2 commits
  4. 13 Feb, 2019 4 commits
  5. 12 Feb, 2019 3 commits
  6. 08 Feb, 2019 3 commits
  7. 06 Feb, 2019 14 commits
  8. 30 Jan, 2019 2 commits
    • Jonas Bonn's avatar
      spi-atmel: support inter-word delay · 473a78a7
      Jonas Bonn authored and Mark Brown's avatar Mark Brown committed
      
      
      If the SPI slave requires an inter-word delay, configure the DLYBCT
      register accordingly.
      
      Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference
      board).
      
      Signed-off-by: default avatarJonas Bonn <jonas@norrbonn.se>
      Acked-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
      CC: Nicolas Ferre <nicolas.ferre@microchip.com>
      CC: Mark Brown <broonie@kernel.org>
      CC: Alexandre Belloni <alexandre.belloni@bootlin.com>
      CC: Ludovic Desroches <ludovic.desroches@microchip.com>
      CC: linux-spi@vger.kernel.org
      CC: linux-arm-kernel@lists.infradead.org
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      473a78a7
    • Jonas Bonn's avatar
      spi: support inter-word delay requirement for devices · b7bb367a
      Jonas Bonn authored and Mark Brown's avatar Mark Brown committed
      
      
      Some devices are slow and cannot keep up with the SPI bus and therefore
      require a short delay between words of the SPI transfer.
      
      The example of this that I'm looking at is a SAMA5D2 with a minimum SPI
      clock of 400kHz talking to an AVR-based SPI slave.  The AVR cannot put
      bytes on the bus fast enough to keep up with the SoC's SPI controller
      even at the lowest bus speed.
      
      This patch introduces the ability to specify a required inter-word
      delay for SPI devices.  It is up to the controller driver to configure
      itself accordingly in order to introduce the requested delay.
      
      Note that, for spi_transfer, there is already a field word_delay that
      provides similar functionality.  This field, however, is specified in
      clock cycles (and worse, SPI controller cycles, not SCK cycles); that
      makes this value dependent on the master clock instead of the device
      clock for which the delay is intended to provide some relief.  This
      patch leaves this old word_delay in place and provides a time-based
      word_delay_us alongside it; the new field fits in the struct padding
      so struct size is constant.  There is only one in-kernel user of the
      word_delay field and presumably that driver could be reworked to use
      the time-based value instead.
      
      The time-based delay is limited to 8 bits as these delays are intended
      to be short.  The SAMA5D2 that I've tested this on limits delays to a
      maximum of ~100us, which is already many word-transfer periods even at
      the minimum transfer speed supported by the controller.
      
      Signed-off-by: default avatarJonas Bonn <jonas@norrbonn.se>
      CC: Mark Brown <broonie@kernel.org>
      CC: Rob Herring <robh+dt@kernel.org>
      CC: Mark Rutland <mark.rutland@arm.com>
      CC: linux-spi@vger.kernel.org
      CC: devicetree@vger.kernel.org
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      b7bb367a
  9. 29 Jan, 2019 4 commits
  10. 28 Jan, 2019 5 commits