1. 28 Jan, 2019 5 commits
  2. 24 Jan, 2019 4 commits
  3. 23 Jan, 2019 3 commits
  4. 21 Jan, 2019 1 commit
  5. 18 Jan, 2019 3 commits
  6. 17 Jan, 2019 4 commits
  7. 14 Jan, 2019 3 commits
    • Charles Keepax's avatar
      spi: cadence: Correct initialisation of runtime PM · 734882a8
      Charles Keepax authored and Mark Brown's avatar Mark Brown committed
      Currently the driver calls pm_runtime_put_autosuspend but without ever
      having done a pm_runtime_get, this causes the reference count in the pm
      runtime core to become -1. The bad reference count causes the core to
      sometimes suspend whilst an active SPI transfer is in progress.
      
      arizona spi0.1: SPI transfer timed out
      spi_master spi0: failed to transfer one message from queue
      
      The correct proceedure is to do all the initialisation that requires the
      hardware to be powered up before enabling the PM runtime, then enable
      the PM runtime having called pm_runtime_set_active to inform it that the
      hardware is currently powered up. The core will then power it down at
      it's leisure and no explicit pm_runtime_put is required.
      
      Fixes: d36ccd9f
      
       ("spi: cadence: Runtime pm adaptation")
      Signed-off-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      734882a8
    • Stephen Boyd's avatar
      spi: spi-geni-qcom: Get rid of forward declaration · de43affe
      Stephen Boyd authored and Mark Brown's avatar Mark Brown committed
      
      
      We don't need this forward declaration. Move the function to where it
      needed so we can drop it and shave some lines of code.
      
      CC: Girish Mahadevan <girishm@codeaurora.org>
      CC: Dilip Kota <dkota@codeaurora.org>
      CC: Alok Chauhan <alokc@codeaurora.org>
      Cc: Douglas Anderson <dianders@chromium.org>
      Signed-off-by: default avatarStephen Boyd <swboyd@chromium.org>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      de43affe
    • Stephen Boyd's avatar
      spi: spi-geni-qcom: Don't initialize completion for normal message · 0357a3da
      Stephen Boyd authored and Mark Brown's avatar Mark Brown committed
      
      
      We only use this completion when we're doing something that isn't a
      message transfer. For example, changing CS or aborting/canceling a
      command. All of those situations properly reinitialize the completion
      before sending the GENI the special command to change CS or cancel, etc.
      Given that, let's remove the initialization here.
      
      Cc: Girish Mahadevan <girishm@codeaurora.org>
      Cc: Dilip Kota <dkota@codeaurora.org>
      Cc: Alok Chauhan <alokc@codeaurora.org>
      Cc: Douglas Anderson <dianders@chromium.org>
      Signed-off-by: default avatarStephen Boyd <swboyd@chromium.org>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      0357a3da
  8. 10 Jan, 2019 2 commits
  9. 09 Jan, 2019 8 commits
    • Martin Sperl's avatar
      spi: core: avoid waking pump thread from spi_sync instead run teardown delayed · 412e6037
      Martin Sperl authored and Mark Brown's avatar Mark Brown committed
      
      
      When spi_sync is running alone with no other spi devices connected
      to the bus the worker thread is woken during spi_finalize_current_message
      to run the teardown code every time.
      
      This is totally unnecessary in the case that there is no message queued.
      
      On a multi-core system this results in one wakeup of the thread for each
      spi_message processed via spi_sync where in most cases the teardown does
      not happen as the hw is already in use.
      
      This patch now delays the teardown by 1 second by using a separate
      kthread_delayed_work for the teardown.
      
      This avoids waking the kthread too often.
      
      For spi_sync transfers in a tight loop (say 40k messages/s) this
      avoids the penalty of waking the worker thread 40k times/s.
      On a rasperry pi 3 with 4 cores the results in 32% of a single core
      only to find out that there is nothing in the queue and it can go back
      to sleep.
      
      With this patch applied the spi-worker is woken exactly once: after
      the load finishes and the spi bus is idle for 1 second.
      
      I believe I have also seen situations where during a spi_sync loop
      the worker thread (triggered by the last message finished) is slightly
      faster and _wins_ the race to process the message, so we are actually
      running the kthread and letting it do some work...
      
      This is also no longer observed with this patch applied as.
      
      Tested with a new CAN controller driver for the mcp2517fd which
      uses spi_sync for interrupt handling and spi_async for scheduling
      of can frames for transmission (in a different thread)
      
      Some statistics when receiving 100000 CAN frames with the mcp25xxfd driver
      on a Raspberry pi 3:
      
      without the patch:
      ------------------
      root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done
      (spi0)                    5
      (irq/94-mcp25xxf)         0
      root@raspcm3:~# vmstat 1
      procs -----------memory---------- ---swap-- -----io---- -system-- ------cpu-----
       r  b   swpd   free   buff  cache   si   so    bi    bo   in   cs us sy id wa st
       1  0      0 821960  13592  50848    0    0    80     2 1986  105  1  2 97  0  0
       0  0      0 821968  13592  50876    0    0     0     0 8046   30  0  0 100  0  0
       0  0      0 821936  13592  50876    0    0     0     0 8032   24  0  0 100  0  0
       0  0      0 821936  13592  50876    0    0     0     0 8035   30  0  0 100  0  0
       0  0      0 821936  13592  50876    0    0     0     0 8033   22  0  0 100  0  0
       2  0      0 821936  13592  50876    0    0     0     0 11598 7129  0  3 97  0  0
       1  0      0 821872  13592  50876    0    0     0     0 37741 59003  0 31 69  0  0
       2  0      0 821840  13592  50876    0    0     0     0 37762 59078  0 29 71  0  0
       2  0      0 821776  13592  50876    0    0     0     0 37593 58792  0 28 72  0  0
       1  0      0 821744  13592  50876    0    0     0     0 37642 58881  0 30 70  0  0
       2  0      0 821680  13592  50876    0    0     0     0 37490 58602  0 27 73  0  0
       1  0      0 821648  13592  50876    0    0     0     0 37412 58418  0 29 71  0  0
       1  0      0 821584  13592  50876    0    0     0     0 37337 58288  0 27 73  0  0
       1  0      0 821552  13592  50876    0    0     0     0 37584 58774  0 27 73  0  0
       0  0      0 821520  13592  50876    0    0     0     0 18363 20566  0  9 91  0  0
       0  0      0 821520  13592  50876    0    0     0     0 8037   32  0  0 100  0  0
       0  0      0 821520  13592  50876    0    0     0     0 8031   23  0  0 100  0  0
       0  0      0 821520  13592  50876    0    0     0     0 8034   26  0  0 100  0  0
       0  0      0 821520  13592  50876    0    0     0     0 8033   24  0  0 100  0  0
      ^C
      root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done
      (spi0)                  228
      (irq/94-mcp25xxf)       794
      root@raspcm3:~# cat /proc/interrupts
                 CPU0       CPU1       CPU2       CPU3
       17:         34          0          0          0  ARMCTRL-level   1 Edge      3f00b880.mailbox
       27:          1          0          0          0  ARMCTRL-level  35 Edge      timer
       33:    1416870          0          0          0  ARMCTRL-level  41 Edge      3f980000.usb, dwc2_hsotg:usb1
       34:          1          0          0          0  ARMCTRL-level  42 Edge      vc4
       35:          0          0          0          0  ARMCTRL-level  43 Edge      3f004000.txp
       40:       1753          0          0          0  ARMCTRL-level  48 Edge      DMA IRQ
       42:         11          0          0          0  ARMCTRL-level  50 Edge      DMA IRQ
       44:         11          0          0          0  ARMCTRL-level  52 Edge      DMA IRQ
       45:          0          0          0          0  ARMCTRL-level  53 Edge      DMA IRQ
       66:          0          0          0          0  ARMCTRL-level  74 Edge      vc4 crtc
       69:          0          0          0          0  ARMCTRL-level  77 Edge      vc4 crtc
       70:          0          0          0          0  ARMCTRL-level  78 Edge      vc4 crtc
       77:         20          0          0          0  ARMCTRL-level  85 Edge      3f205000.i2c, 3f804000.i2c, 3f805000.i2c
       78:       6346          0          0          0  ARMCTRL-level  86 Edge      3f204000.spi
       80:        205          0          0          0  ARMCTRL-level  88 Edge      mmc0
       81:        493          0          0          0  ARMCTRL-level  89 Edge      uart-pl011
       89:          0          0          0          0  bcm2836-timer   0 Edge      arch_timer
       90:       4291       3821       2180       1649  bcm2836-timer   1 Edge      arch_timer
       94:      14289          0          0          0  pinctrl-bcm2835  16 Level     mcp25xxfd
      IPI0:          0          0          0          0  CPU wakeup interrupts
      IPI1:          0          0          0          0  Timer broadcast interrupts
      IPI2:       3645     242371       7919       1328  Rescheduling interrupts
      IPI3:        112        543        273        194  Function call interrupts
      IPI4:          0          0          0          0  CPU stop interrupts
      IPI5:          1          0          0          0  IRQ work interrupts
      IPI6:          0          0          0          0  completion interrupts
      Err:          0
      
      top shows 93% for the mcp25xxfd interrupt handler, 31% for spi0.
      
      with the patch:
      ---------------
      root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done
      (spi0)                    0
      (irq/94-mcp25xxf)         0
      root@raspcm3:~# vmstat 1
      procs -----------memory---------- ---swap-- -----io---- -system-- ------cpu-----
       0  0      0 804768  13584  62628    0    0     0     0 8038   24  0  0 100  0  0
       0  0      0 804768  13584  62628    0    0     0     0 8042   25  0  0 100  0  0
       1  0      0 804704  13584  62628    0    0     0     0 9603 2967  0 20 80  0  0
       1  0      0 804672  13584  62628    0    0     0     0 9828 3380  0 24 76  0  0
       1  0      0 804608  13584  62628    0    0     0     0 9823 3375  0 23 77  0  0
       1  0      0 804608  13584  62628    0    0     0    12 9829 3394  0 23 77  0  0
       1  0      0 804544  13584  62628    0    0     0     0 9816 3362  0 22 78  0  0
       1  0      0 804512  13584  62628    0    0     0     0 9817 3367  0 23 77  0  0
       1  0      0 804448  13584  62628    0    0     0     0 9822 3370  0 22 78  0  0
       1  0      0 804416  13584  62628    0    0     0     0 9815 3367  0 23 77  0  0
       0  0      0 804352  13584  62628    0    0     0    84 9222 2250  0 14 86  0  0
       0  0      0 804352  13592  62620    0    0     0    24 8131  209  0  0 93  7  0
       0  0      0 804320  13592  62628    0    0     0     0 8041   27  0  0 100  0  0
       0  0      0 804352  13592  62628    0    0     0     0 8040   26  0  0 100  0  0
      root@raspcm3:~# for x in $(pgrep spi0) $(pgrep irq/94-mcp25xxf) ; do awk '{printf "%-20s %6i\n", $2,$15}' /proc/$x/stat; done
      (spi0)                    0
      (irq/94-mcp25xxf)       767
      root@raspcm3:~# cat /proc/interrupts
                 CPU0       CPU1       CPU2       CPU3
       17:         29          0          0          0  ARMCTRL-level   1 Edge      3f00b880.mailbox
       27:          1          0          0          0  ARMCTRL-level  35 Edge      timer
       33:    1024412          0          0          0  ARMCTRL-level  41 Edge      3f980000.usb, dwc2_hsotg:usb1
       34:          1          0          0          0  ARMCTRL-level  42 Edge      vc4
       35:          0          0          0          0  ARMCTRL-level  43 Edge      3f004000.txp
       40:       1773          0          0          0  ARMCTRL-level  48 Edge      DMA IRQ
       42:         11          0          0          0  ARMCTRL-level  50 Edge      DMA IRQ
       44:         11          0          0          0  ARMCTRL-level  52 Edge      DMA IRQ
       45:          0          0          0          0  ARMCTRL-level  53 Edge      DMA IRQ
       66:          0          0          0          0  ARMCTRL-level  74 Edge      vc4 crtc
       69:          0          0          0          0  ARMCTRL-level  77 Edge      vc4 crtc
       70:          0          0          0          0  ARMCTRL-level  78 Edge      vc4 crtc
       77:         20          0          0          0  ARMCTRL-level  85 Edge      3f205000.i2c, 3f804000.i2c, 3f805000.i2c
       78:       6417          0          0          0  ARMCTRL-level  86 Edge      3f204000.spi
       80:        237          0          0          0  ARMCTRL-level  88 Edge      mmc0
       81:        489          0          0          0  ARMCTRL-level  89 Edge      uart-pl011
       89:          0          0          0          0  bcm2836-timer   0 Edge      arch_timer
       90:       4048       3704       2383       1892  bcm2836-timer   1 Edge      arch_timer
       94:      14287          0          0          0  pinctrl-bcm2835  16 Level     mcp25xxfd
      IPI0:          0          0          0          0  CPU wakeup interrupts
      IPI1:          0          0          0          0  Timer broadcast interrupts
      IPI2:       2361       2948       7890       1616  Rescheduling interrupts
      IPI3:         65        617        301        166  Function call interrupts
      IPI4:          0          0          0          0  CPU stop interrupts
      IPI5:          1          0          0          0  IRQ work interrupts
      IPI6:          0          0          0          0  completion interrupts
      Err:          0
      top shows 91% for the mcp25xxfd interrupt handler, 0% for spi0
      
      So we see that spi0 is no longer getting scheduled wasting CPU cycles
      There are a lot less context switches and corresponding Rescheduling interrupts
      All of these show that this improves efficiency of the system and reduces
      CPU utilization.
      
      Signed-off-by: default avatarMartin Sperl <kernel@martin.sperl.org>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      412e6037
    • Linus Walleij's avatar
      spi: dw: Convert to use CS GPIO descriptors · 9400c41e
      Linus Walleij authored and Mark Brown's avatar Mark Brown committed
      
      
      This converts the DesignWare (dw) SPI master driver to
      use GPIO descriptors for chip select handling.
      
      This driver has a duplicate DT parser in addition to the
      one in the core, sets up the line as non-asserted and
      relies on the core to drive the GPIOs.
      
      It is a pretty straight-forward conversion.
      
      Cc: Talel Shenhar <talel@amazon.com>
      Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
      Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
      Cc: Linuxarm <linuxarm@huawei.com>
      Tested-by: default avatarJay Fang <f.fangjian@huawei.com>
      Reviewed-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      9400c41e
    • Linus Walleij's avatar
      spi: davinci: Convert to use CS GPIO descriptors · 101a68e7
      Linus Walleij authored and Mark Brown's avatar Mark Brown committed
      
      
      This converts the DaVinci SPI master driver to use GPIO
      descriptors for chip select handling.
      
      DaVinci parses the device tree a second time for the chip
      select GPIOs (no relying on the parsing already happening
      in the SPI core) and handles inversion semantics locally.
      
      We simply drop the extra parsing and set up and move the
      CS handling to the core and gpiolib. The fact that the
      driver is actively driving the GPIO in the
      davinci_spi_chipselect() callback is confusing since the
      host does not set SPI_MASTER_GPIO_SS so this should not
      ever get called when using GPIO CS. I put in a comment
      about this.
      
      This driver also supports instantiation from board files,
      but these are all using native chip selects so no problem
      with GPIO lines here.
      
      Cc: David Lechner <david@lechnology.com>
      Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
      Cc: Linuxarm <linuxarm@huawei.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      101a68e7
    • Linus Walleij's avatar
      spi: clps711x: Convert to use CS GPIO descriptors · 054320b2
      Linus Walleij authored and Mark Brown's avatar Mark Brown committed
      
      
      This converts the CLPS711x SPI master driver to use GPIO
      descriptors for chip select handling.
      
      The CLPS711x driver was merely requesting the GPIO and
      setting the CS line non-asserted so this was a pretty
      straight-forward conversion. The setup callback goes away.
      
      Cc: Alexander Shiyan <shc_work@mail.ru>
      Cc: Linuxarm <linuxarm@huawei.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      054320b2
    • Linus Walleij's avatar
      spi: cadence: Convert to use CS GPIO descriptors · cfeefa79
      Linus Walleij authored and Mark Brown's avatar Mark Brown committed
      
      
      This converts the Cadence SPI master driver to use GPIO
      descriptors for chip select handling.
      
      The Cadence driver was allocating a state container just
      to hold the requested GPIO line and contained lots of
      polarity inversion code. As this is all handled by gpiolib
      and a simple devm_* request in the core, and as the driver
      is fully device tree only, most of this code chunk goes
      away in favour of central handling. The setup/cleanup
      callbacks goes away.
      
      This driver does NOT drive the CS line by setting the
      value of the GPIO so it relies on the SPI core to do
      this, which should work just fine with the descriptors.
      
      Cc: Wei Yongjun <weiyongjun1@huawei.com>
      Cc: Janek Kotas <jank@cadence.com>
      Cc: Linuxarm <linuxarm@huawei.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      cfeefa79
    • Linus Walleij's avatar
      spi: atmel: Convert to use CS GPIO descriptors · efc92fbb
      Linus Walleij authored and Mark Brown's avatar Mark Brown committed
      
      
      This converts the Atmel SPI master driver to use GPIO descriptors
      for chip select handling.
      
      The Atmel driver has duplicate code to look up and initialize CS
      GPIOs from the device tree, so this is removed. It further has code
      to retrieve a CS GPIO from .controller_data but this seems to be
      completely unused in the kernel (legacy codepath?) so I deleted
      this support. It keeps track of polarity when switching the CS, but
      this is not needed anymore since we moved this over to the gpiolib.
      
      The local handling of the "npcs_pin" (I guess this might mean
      "negative polarity chip select pin") is preserved, but I strongly
      suspect this can be switched over to handling by the core and
      using the SPI_MASTER_GPIO_SS flag on the master to assure that
      the additional CS handling in the driver is also done.
      
      Cc: Eugen Hristev <eugen.hristev@microchip.com>
      Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
      Cc: Radu Pirea <radu.pirea@microchip.com>
      Cc: Linuxarm <linuxarm@huawei.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      efc92fbb
    • Linus Walleij's avatar
      spi: ath79: Convert to use CS GPIO descriptors · 8db79547
      Linus Walleij authored and Mark Brown's avatar Mark Brown committed
      
      
      This converts the ATH79 SPI master driver to use GPIO descriptors
      for chip select handling.
      
      The ATH79 driver was requesting the GPIO and driving it from the
      bitbang .chipselect callback. Do not request it anymore as the SPI
      core will request it, remove the line inversion semantics for the
      GPIO case (handled by gpiolib) and let the SPI core deal with
      requesting the GPIO line from the device tree node of the controller.
      
      This driver can be instantiated from a board file (no device tree)
      but the board files only use native CS (no GPIO lines) so we should
      be fine just letting the SPI core grab the GPIO from the device.
      
      The fact that the driver is actively driving the GPIO in the
      ath79_spi_chipselect() callback is confusing since the host does
      not set SPI_MASTER_GPIO_SS so this should not ever get called when
      using GPIO CS. I put in a comment about this.
      
      Cc: Felix Fietkau <nbd@nbd.name>
      Cc: Alban Bedel <albeu@free.fr>
      Cc: Linuxarm <linuxarm@huawei.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      8db79547
    • Linus Walleij's avatar
      spi: Optionally use GPIO descriptors for CS GPIOs · f3186dd8
      Linus Walleij authored and Mark Brown's avatar Mark Brown committed
      This augments the SPI core to optionally use GPIO descriptors
      for chip select on a per-master-driver opt-in basis.
      
      Drivers using this will rely on the SPI core to look up
      GPIO descriptors associated with the device, such as
      when using device tree or board files with GPIO descriptor
      tables.
      
      When getting descriptors from the device tree, this will in
      turn activate the code in gpiolib that was
      added in commit 6953c57a
      
      
      ("gpio: of: Handle SPI chipselect legacy bindings")
      which means that these descriptors are aware of the active
      low semantics that is the default for SPI CS GPIO lines
      and we can assume that all of these are "active high" and
      thus assign SPI_CS_HIGH to all CS lines on the DT path.
      
      The previously used gpio_set_value() would call down into
      gpiod_set_raw_value() and ignore the polarity inversion
      semantics.
      
      It seems like many drivers go to great lengths to set up the
      CS GPIO line as non-asserted, respecting SPI_CS_HIGH. We pull
      this out of the SPI drivers and into the core, and by simply
      requesting the line as GPIOD_OUT_LOW when retrieveing it from
      the device and relying on the gpiolib to handle any inversion
      semantics. This way a lot of code can be simplified and
      removed in each converted driver.
      
      The end goal after dealing with each driver in turn, is to
      delete the non-descriptor path (of_spi_register_master() for
      example) and let the core deal with only descriptors.
      
      The different SPI drivers have complex interactions with the
      core so we cannot simply change them all over, we need to use
      a stepwise, bisectable approach so that each driver can be
      converted and fixed in isolation.
      
      This patch has the intended side effect of adding support for
      ACPI GPIOs as it starts relying on gpiod_get_*() to get
      the GPIO handle associated with the device.
      
      Cc: Linuxarm <linuxarm@huawei.com>
      Acked-by: default avatarJonathan Cameron <jonathan.cameron@huawei.com>
      Tested-by: default avatarFangjian (Turing) <f.fangjian@huawei.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      f3186dd8
  10. 07 Jan, 2019 7 commits