1. 01 Sep, 2019 1 commit
  2. 17 Dec, 2017 1 commit
  3. 11 Mar, 2016 1 commit
    • Max Filippov's avatar
      xtensa: support hardware breakpoints/watchpoints · c91e02bd
      Max Filippov authored
      
      
      Use perf framework to manage hardware instruction and data breakpoints.
      Add two new ptrace calls: PTRACE_GETHBPREGS and PTRACE_SETHBPREGS to
      query and set instruction and data breakpoints.
      Address bit 0 choose instruction (0) or data (1) break register, bits
      31..1 are the register number.
      Both calls transfer two 32-bit words: address (0) and control (1).
      Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set.
      Data breakpoint control word bit 31 is 'trigger on store', bit 30 is
      'trigger on load, bits 29..0 are length. Length 0 is used to clear a
      breakpoint. To set a breakpoint length must be a power of 2 in the range
      1..64 and the address must be length-aligned.
      
      Introduce new thread_info flag: TIF_DB_DISABLED. Set it if debug
      exception is raised by the kernel code accessing watched userspace
      address and disable corresponding data breakpoint. On exit to userspace
      check that flag and, if set, restore all data breakpoints.
      
      Handle debug exceptions raised with PS.EXCM set. This may happen when
      window overflow/underflow handler or fast exception handler hits data
      breakpoint, in which case save and disable all data breakpoints,
      single-step faulting instruction and restore data breakpoints.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      c91e02bd
  4. 06 Sep, 2013 1 commit
  5. 24 Feb, 2013 1 commit
  6. 19 Dec, 2012 2 commits
    • Chris Zankel's avatar
      xtensa: clean up files to make them code-style compliant · c4c4594b
      Chris Zankel authored
      
      
      Remove heading and trailing spaces, trim trailing lines, and wrap lines
      that are longer than 80 characters.
      Signed-off-by: default avatarChris Zankel <chris@zankel.net>
      c4c4594b
    • Max Filippov's avatar
      xtensa: add s32c1i sanity check · 00273125
      Max Filippov authored
      
      
      Add a brief sanity test of S32C1I functionality.  This instruction
      is needed by the kernel and userland as part of the base ABI
      (including GCC atomic builtins, certain threading packages, future
      atomic support in the C++ standard, etc).  However, correct operation
      of this instruction requires some cooperation by hardware external to
      the processor (such as bus bridge, bus fabric, or memory controller).
      Minimally exercising this mechanism and reporting explicit status
      early in the boot process is helpful to chip vendors using the Linux
      kernel as a benchmark of correctness of hardware.
      
      As it turns out, S32C1I is not exercised by the kernel and by uClibc
      based userland as of early June 2008.  This is expected to change
      soon as both incorporate more recent open source developments.
      Signed-off-by: default avatarMarc Gauthier <marc@tensilica.com>
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      Signed-off-by: default avatarChris Zankel <chris@zankel.net>
      00273125
  7. 16 Oct, 2012 1 commit
  8. 03 Oct, 2012 1 commit
  9. 06 Nov, 2008 1 commit
  10. 14 Feb, 2008 1 commit
    • Chris Zankel's avatar
      [XTENSA] Add support for configurable registers and coprocessors · c658eac6
      Chris Zankel authored
      
      
      The Xtensa architecture allows to define custom instructions and
      registers. Registers that are bound to a coprocessor are only
      accessible if the corresponding enable bit is set, which allows
      to implement a 'lazy' context switch mechanism. Other registers
      needs to be saved and restore at the time of the context switch
      or during interrupt handling.
      
      This patch adds support for these additional states:
      
      - save and restore registers that are used by the compiler upon
        interrupt entry and exit.
      - context switch additional registers unbound to any coprocessor
      - 'lazy' context switch of registers bound to a coprocessor
      - ptrace interface to provide access to additional registers
      - update configuration files in include/asm-xtensa/variant-fsf
      Signed-off-by: default avatarChris Zankel <chris@zankel.net>
      c658eac6
  11. 10 Dec, 2006 1 commit