1. 01 Sep, 2019 2 commits
    • Max Filippov's avatar
      xtensa: add support for call0 ABI in userspace · 09f8a6db
      Max Filippov authored
      Provide a Kconfig choice to select whether only the default ABI, only
      call0 ABI or both are supported. The default for XEA2 is windowed, but
      it may change for XEA3. Call0 only runs userspace with PS.WOE disabled.
      Supporting both windowed and call0 ABIs is tricky, as there's no
      indication in the ELF binaries which ABI they use. So it is done by
      probing: each process is started with PS.WOE disabled, but the handler
      of an illegal instruction exception taken with PS.WOE retries faulting
      instruction after enabling PS.WOE. It must happen before any signal is
      delivered to the process, otherwise it may be delivered incorrectly.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    • Max Filippov's avatar
      xtensa: clean up PS_WOE_BIT usage · 9e1e41c4
      Max Filippov authored
      PS_WOE_BIT is mainly used to generate PS.WOE mask in the code. Introduce
      PS_WOE_MASK macro and use it instead.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
  2. 08 Jul, 2019 1 commit
    • Max Filippov's avatar
      xtensa: abstract 'entry' and 'retw' in assembly code · d6d5f19e
      Max Filippov authored
      Provide abi_entry, abi_entry_default, abi_ret and abi_ret_default macros
      that allocate aligned stack frame in windowed and call0 ABIs.
      Provide XTENSA_SPILL_STACK_RESERVE macro that specifies required stack
      frame size when register spilling is involved.
      Replace all uses of 'entry' and 'retw' with the above macros.
      This makes most of the xtensa assembly code ready for XEA3 and call0 ABI.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
  3. 04 Apr, 2019 1 commit
  4. 17 Dec, 2018 2 commits
  5. 03 Dec, 2018 2 commits
    • Max Filippov's avatar
      xtensa: drop fast_syscall_kernel · 8ed3a542
      Max Filippov authored
      There must be no xtensa-specific syscalls from the kernel code: register
      spilling uses call+entry sequence and atomics have proper function
      implementations. Drop fast_syscall_xtensa.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    • Firoz Khan's avatar
      xtensa: add __NR_syscalls along with __NR_syscall_count · a86067f5
      Firoz Khan authored
      __NR_syscall_count macro holds the number of system call
      exist in xtensa architecture. We have to change the value
      of __NR_syscall_count, if we add or delete a system call.
      One of the patch in this patch series has a script which
      will generate a uapi header based on syscall.tbl file.
      The syscall.tbl file contains the total number of system
      calls information. So we have two option to update __NR-
      _syscall_count value.
      1. Update __NR_syscall_count in asm/unistd.h manually by
         counting the no.of system calls. No need to update __NR-
         _syscall_count until we either add a new system call or
         delete existing system call.
      2. We can keep this feature it above mentioned script,
         that will count the number of syscalls and keep it in
         a generated file. In this case we don't need to expli-
         citly update __NR_syscall_count in asm/unistd.h file.
      The 2nd option will be the recommended one. For that, I
      added the __NR_syscalls macro in uapi/asm/unistd.h.
      The macro __NR_syscalls also added for making the name
      convention same across all architecture. While __NR_syscalls
      isn't strictly part of the uapi, having it as part of the
      generated header to simplifies the implementation. We also
      need to enclose this macro with #ifdef __KERNEL__ to avoid
      side effects.
      Signed-off-by: default avatarFiroz Khan <firoz.khan@linaro.org>
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      [Max: Drop __NR_syscall_count completely, use __NR_syscalls instead]
  6. 14 Jun, 2018 1 commit
    • Linus Torvalds's avatar
      Kbuild: rename CC_STACKPROTECTOR[_STRONG] config variables · 050e9baa
      Linus Torvalds authored
      The changes to automatically test for working stack protector compiler
      support in the Kconfig files removed the special STACKPROTECTOR_AUTO
      option that picked the strongest stack protector that the compiler
      That was all a nice cleanup - it makes no sense to have the AUTO case
      now that the Kconfig phase can just determine the compiler support
      It also meant that doing "make oldconfig" would now _disable_ the strong
      stackprotector if you had AUTO enabled, because in a legacy config file,
      the sane stack protector configuration would look like
      and when you ran this through "make oldconfig" with the Kbuild changes,
      it would ask you about the regular CONFIG_CC_STACKPROTECTOR (that had
      been renamed from CONFIG_CC_STACKPROTECTOR_REGULAR to just
      CONFIG_CC_STACKPROTECTOR), but it would think that the STRONG version
      used to be disabled (because it was really enabled by AUTO), and would
      disable it in the new config, resulting in:
      That's dangerously subtle - people could suddenly find themselves with
      the weaker stack protector setup without even realizing.
      The solution here is to just rename not just the old RECULAR stack
      protector option, but also the strong one.  This does that by just
      removing the CC_ prefix entirely for the user choices, because it really
      is not about the compiler support (the compiler support now instead
      automatially impacts _visibility_ of the options to users).
      This results in "make oldconfig" actually asking the user for their
      choice, so that we don't have any silent subtle security model changes.
      The end result would generally look like this:
      where the "CC_" versions really are about internal compiler
      infrastructure, not the user selections.
      Acked-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
  7. 17 Dec, 2017 1 commit
  8. 10 Dec, 2017 3 commits
  9. 01 May, 2017 1 commit
  10. 28 Sep, 2016 1 commit
  11. 24 Jul, 2016 1 commit
    • Max Filippov's avatar
      xtensa: cleanup MMU setup and kernel layout macros · a9f2fc62
      Max Filippov authored
      Make kernel load address explicit, independent of the selected MMU
      configuration and configurable from Kconfig. Do not restrict it to the
      first 512MB of the physical address space.
      Cleanup kernel memory layout macros:
      - introduce PHYS_OFFSET and use it in __va and __pa definitions;
      - synchronize MMU/noMMU vectors, drop unused NMI vector;
      - replace hardcoded vectors offset of 0x3000 with Kconfig symbol.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
  12. 11 Mar, 2016 2 commits
    • Max Filippov's avatar
      xtensa: support hardware breakpoints/watchpoints · c91e02bd
      Max Filippov authored
      Use perf framework to manage hardware instruction and data breakpoints.
      Add two new ptrace calls: PTRACE_GETHBPREGS and PTRACE_SETHBPREGS to
      query and set instruction and data breakpoints.
      Address bit 0 choose instruction (0) or data (1) break register, bits
      31..1 are the register number.
      Both calls transfer two 32-bit words: address (0) and control (1).
      Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set.
      Data breakpoint control word bit 31 is 'trigger on store', bit 30 is
      'trigger on load, bits 29..0 are length. Length 0 is used to clear a
      breakpoint. To set a breakpoint length must be a power of 2 in the range
      1..64 and the address must be length-aligned.
      Introduce new thread_info flag: TIF_DB_DISABLED. Set it if debug
      exception is raised by the kernel code accessing watched userspace
      address and disable corresponding data breakpoint. On exit to userspace
      check that flag and, if set, restore all data breakpoints.
      Handle debug exceptions raised with PS.EXCM set. This may happen when
      window overflow/underflow handler or fast exception handler hits data
      breakpoint, in which case save and disable all data breakpoints,
      single-step faulting instruction and restore data breakpoints.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    • Max Filippov's avatar
      xtensa: use context structure for debug exceptions · 6ec7026a
      Max Filippov authored
      With implementation of data breakpoints debug exceptions raised when
      PS.EXCM is set need to be handled, e.g. window overflow code can write
      to watched userspace address. Currently debug exception handler uses
      EXCSAVE and DEPC SRs to save temporary registers, but DEPC may not be
      available when PS.EXCM is set and more space will be needed to save
      additional state.
      Reorganize debug context: create per-CPU structure debug_table instance
      and store its address in the EXCSAVE<debug level> instead of
      debug_exception function address. Expand this structure when more save
      space is needed.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
  13. 02 Nov, 2015 1 commit
    • Max Filippov's avatar
      xtensa: fixes for configs without loop option · 5029615e
      Max Filippov authored
      Build-time fixes:
      - make lbeg/lend/lcount save/restore conditional on kernel entry;
      - don't clear lcount in platform_restart functions unconditionally.
      Run-time fixes:
      - use correct end of range register in __endla paired with __loopt, not
        the unused temporary register. This fixes .bss zero-initialization.
        Update comments in asmmacro.h;
      - don't clobber a10 in the usercopy that leads to access to unmapped
      Cc: <stable@vger.kernel.org>
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
  14. 17 Aug, 2015 5 commits
    • Max Filippov's avatar
      xtensa: implement fake NMI · 38fef73c
      Max Filippov authored
      In case perf IRQ is the highest of the medium-level IRQs, and is alone
      on its level, it may be treated as NMI:
      - LOCKLEVEL is defined to be one level less than EXCM level,
      - IRQ masking never lowers current IRQ level,
      - new fake exception cause code, EXCCAUSE_MAPPED_NMI is assigned to that
        IRQ; new second level exception handler, do_nmi, assigned to it
        handles it as NMI,
      - atomic operations in configurations without s32c1i still need to mask
        all interrupts.
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    • Max Filippov's avatar
      xtensa: don't touch EXC_TABLE_FIXUP in _switch_to · 98e29832
      Max Filippov authored
      There's no way _switch_to can produce double exceptions now, don't
      enter/leave EXC_TABLE_FIXUP critical section.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    • Max Filippov's avatar
      xtensa: fix kernel register spilling · 77d6273e
      Max Filippov authored
      call12 can't be safely used as the first call in the inline function,
      because the compiler does not extend the stack frame of the bounding
      function accordingly, which may result in corruption of local variables.
      If a call needs to be done, do call8 first followed by call12.
      For pure assembly code in _switch_to increase stack frame size of the
      bounding function.
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    • Max Filippov's avatar
      xtensa: reorganize irq flags tracing · 7d5f6a9a
      Max Filippov authored
      entry.s only disables IRQs on hardware IRQ, move trace_hardirqs_off call
      into do_interrupt. Check actual intlevel that will be restored on return
      from exception handler to decide if trace_hardirqs_on should be called.
      Annotate IRQ on/off points in the TIF_* handling loop on return from
      exception handler.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    • Max Filippov's avatar
      xtensa: keep exception/interrupt stack continuous · b6569439
      Max Filippov authored
      Restore original a0 in the kernel exception stack frame. This way it
      looks like the frame that got interrupt/exception did alloca (copy a0 and
      a1 spilled under old stack to the new location as well) to save registers
      and then did a call to handler.
      The point where interrupt/exception was taken is not in the stack chain,
      only in pt_regs (call4 from that address can be simulated to keep it in
      the stack trace).
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
  15. 14 Jul, 2015 1 commit
  16. 14 Aug, 2014 4 commits
    • Max Filippov's avatar
      xtensa: deprecate fast_xtensa and fast_spill_registers syscalls · 9184289c
      Max Filippov authored
      These syscalls are not used by userspace tools for some time now, and
      they have issues when called with invalid arguments. It's not worth
      changing signal delivery mechanism as we don't expect any new users for
      these syscalls. Let's keep them for backwards compatibility under #ifdef,
      disabled by default.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    • Max Filippov's avatar
      xtensa: fix a6 and a7 handling in fast_syscall_xtensa · d1b6ba82
      Max Filippov authored
      Remove restoring a6 on some return paths and instead modify and restore
      it in a single place, using symbolic name.
      Correctly restore a7 from PT_AREG7 in case of illegal a6 value.
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    • Max Filippov's avatar
      xtensa: fix TLBTEMP_BASE_2 region handling in fast_second_level_miss · 7128039f
      Max Filippov authored
      Current definition of TLBTEMP_BASE_2 is always 32K above the
      TLBTEMP_BASE_1, whereas fast_second_level_miss handler for the TLBTEMP
      region analyzes virtual address bit (PAGE_SHIFT + DCACHE_ALIAS_ORDER)
      to determine TLBTEMP region where the fault happened. The size of the
      TLBTEMP region is also checked incorrectly: not 64K, but twice data
      cache way size (whicht may as well be less than the instruction cache
      way size).
      Fix TLBTEMP_BASE_2 to be TLBTEMP_BASE_1 + data cache way size.
      Provide TLBTEMP_SIZE that is a greater of doubled data cache way size or
      the instruction cache way size, and use it to determine if the second
      level TLB miss occured in the TLBTEMP region.
      Practical occurence of page faults in the TLBTEMP area is extremely
      rare, this code can be tested by deletion of all w[di]tlb instructions
      in the tlbtemp_mapping region.
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    • Max Filippov's avatar
      xtensa: fix access to THREAD_RA/THREAD_SP/THREAD_DS · 52247123
      Max Filippov authored
      With SMP and a lot of debug options enabled task_struct::thread gets out
      of reach of s32i/l32i instructions with base pointing at task_struct,
      breaking build with the following messages:
        arch/xtensa/kernel/entry.S: Assembler messages:
        arch/xtensa/kernel/entry.S:1002: Error: operand 3 of 'l32i.n' has invalid value '1048'
        arch/xtensa/kernel/entry.S:1831: Error: operand 3 of 's32i.n' has invalid value '1040'
        arch/xtensa/kernel/entry.S:1832: Error: operand 3 of 's32i.n' has invalid value '1044'
      Change base to point to task_struct::thread in such cases.
      Don't use a10 in _switch_to to save/restore prev pointer as a2 is not
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
  17. 29 Jan, 2014 1 commit
    • Chris Zankel's avatar
      xtensa: fix fast_syscall_spill_registers · 6b5a1f74
      Chris Zankel authored
      The original implementation could clobber registers under certain conditions.
      The Xtensa processor architecture uses windowed registers and the original
      implementation was using a4 as a temporary register, which under certain
      conditions could be register a0 of the oldest window frame, and didn't always
      restore the content correctly.
      By moving the _spill_registers routine inside the fast system call, it frees
      up one more register (the return address is not required anymore) for the
      spill routine.
      Signed-off-by: default avatarChris Zankel <chris@zankel.net>
  18. 25 Jan, 2014 2 commits
  19. 15 Oct, 2013 1 commit
  20. 06 Sep, 2013 4 commits
  21. 08 Jul, 2013 1 commit
  22. 20 May, 2013 1 commit
  23. 09 May, 2013 1 commit