1. 01 Sep, 2019 1 commit
  2. 26 Jan, 2019 1 commit
    • Max Filippov's avatar
      xtensa: SMP: fix secondary CPU initialization · 32a7726c
      Max Filippov authored
      
      
      - add missing memory barriers to the secondary CPU synchronization spin
        loops; add comment to the matching memory barrier in the boot_secondary
        and __cpu_die functions;
      - use READ_ONCE/WRITE_ONCE to access cpu_start_id/cpu_start_ccount
        instead of reading/writing them directly;
      - re-initialize cpu_running every time before starting secondary CPU to
        flush possible previous CPU startup results.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      32a7726c
  3. 05 Dec, 2018 1 commit
  4. 14 Nov, 2018 1 commit
    • Max Filippov's avatar
      xtensa: fix boot parameters address translation · 40dc948f
      Max Filippov authored
      
      
      The bootloader may pass physical address of the boot parameters structure
      to the MMUv3 kernel in the register a2. Code in the _SetupMMU block in
      the arch/xtensa/kernel/head.S is supposed to map that physical address to
      the virtual address in the configured virtual memory layout.
      
      This code haven't been updated when additional 256+256 and 512+512
      memory layouts were introduced and it may produce wrong addresses when
      used with these layouts.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      40dc948f
  5. 14 Aug, 2018 1 commit
  6. 10 Dec, 2017 1 commit
  7. 24 Jul, 2016 1 commit
    • Max Filippov's avatar
      xtensa: cleanup MMU setup and kernel layout macros · a9f2fc62
      Max Filippov authored
      
      
      Make kernel load address explicit, independent of the selected MMU
      configuration and configurable from Kconfig. Do not restrict it to the
      first 512MB of the physical address space.
      
      Cleanup kernel memory layout macros:
      
      - rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR;
      - drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS;
      - introduce PHYS_OFFSET and use it in __va and __pa definitions;
      - synchronize MMU/noMMU vectors, drop unused NMI vector;
      - replace hardcoded vectors offset of 0x3000 with Kconfig symbol.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      a9f2fc62
  8. 11 Mar, 2016 2 commits
    • Max Filippov's avatar
      xtensa: use context structure for debug exceptions · 6ec7026a
      Max Filippov authored
      
      
      With implementation of data breakpoints debug exceptions raised when
      PS.EXCM is set need to be handled, e.g. window overflow code can write
      to watched userspace address. Currently debug exception handler uses
      EXCSAVE and DEPC SRs to save temporary registers, but DEPC may not be
      available when PS.EXCM is set and more space will be needed to save
      additional state.
      Reorganize debug context: create per-CPU structure debug_table instance
      and store its address in the EXCSAVE<debug level> instead of
      debug_exception function address. Expand this structure when more save
      space is needed.
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      6ec7026a
    • Max Filippov's avatar
      xtensa: clear all DBREAKC registers on start · 7de7ac78
      Max Filippov authored
      
      
      There are XCHAL_NUM_DBREAK registers, clear them all.
      This also fixes cryptic assembler error message with binutils 2.25 when
      XCHAL_NUM_DBREAK is 0:
      
        as: out of memory allocating 18446744073709551575 bytes after a total
        of 495616 bytes
      
      Cc: stable@vger.kernel.org
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      7de7ac78
  9. 02 Nov, 2015 1 commit
    • Max Filippov's avatar
      xtensa: fixes for configs without loop option · 5029615e
      Max Filippov authored
      
      
      Build-time fixes:
      - make lbeg/lend/lcount save/restore conditional on kernel entry;
      - don't clear lcount in platform_restart functions unconditionally.
      
      Run-time fixes:
      - use correct end of range register in __endla paired with __loopt, not
        the unused temporary register. This fixes .bss zero-initialization.
        Update comments in asmmacro.h;
      - don't clobber a10 in the usercopy that leads to access to unmapped
        memory.
      
      Cc: <stable@vger.kernel.org>
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      5029615e
  10. 21 Oct, 2014 1 commit
  11. 14 Jan, 2014 2 commits
  12. 08 Jul, 2013 1 commit
  13. 09 May, 2013 2 commits
    • Max Filippov's avatar
      xtensa: add MMU v3 support · e85e335f
      Max Filippov authored
      
      
      MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB
      way 6:
      
      Way 6 (512 MB)
              Vaddr       Paddr       ASID  Attr RWX Cache
              ----------  ----------  ----  ---- --- -------
              0x00000000  0x00000000  0x01  0x03 RWX Bypass
              0x20000000  0x20000000  0x01  0x03 RWX Bypass
              0x40000000  0x40000000  0x01  0x03 RWX Bypass
              0x60000000  0x60000000  0x01  0x03 RWX Bypass
              0x80000000  0x80000000  0x01  0x03 RWX Bypass
              0xa0000000  0xa0000000  0x01  0x03 RWX Bypass
              0xc0000000  0xc0000000  0x01  0x03 RWX Bypass
              0xe0000000  0xe0000000  0x01  0x03 RWX Bypass
      
      This patch adds remapping code at the reset vector or at the kernel
      _start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that
      reconfigures MMUv3 as MMUv2:
      
      Way 5 (128 MB)
              Vaddr       Paddr       ASID  Attr RWX Cache
              ----------  ----------  ----  ---- --- -------
              0xd0000000  0x00000000  0x01  0x07 RWX WB
              0xd8000000  0x00000000  0x01  0x03 RWX Bypass
      Way 6 (256 MB)
              Vaddr       Paddr       ASID  Attr RWX Cache
              ----------  ----------  ----  ---- --- -------
              0xe0000000  0xf0000000  0x01  0x07 RWX WB
              0xf0000000  0xf0000000  0x01  0x03 RWX Bypass
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      Signed-off-by: default avatarChris Zankel <chris@zankel.net>
      e85e335f
    • Max Filippov's avatar
      xtensa: fix ibreakenable register update · d83ff0bb
      Max Filippov authored
      
      
      Only set the register when there is at least one ibreak register,
      otherwise the build fails:
      	arch/xtensa/kernel/head.S:105: Error: invalid register 'ibreakenable'
      	for 'wsr' instruction
      	arch/xtensa/platforms/iss/setup.c:67: Error: invalid register
      	'ibreakenable' for 'wsr' instruction
      Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      Signed-off-by: default avatarChris Zankel <chris@zankel.net>
      d83ff0bb
  14. 24 Feb, 2013 1 commit
  15. 19 Dec, 2012 4 commits
  16. 16 Oct, 2012 1 commit
  17. 02 May, 2010 1 commit
  18. 21 Sep, 2009 1 commit
  19. 26 Apr, 2009 1 commit
  20. 03 Apr, 2009 2 commits
  21. 01 Jun, 2007 1 commit
  22. 10 Dec, 2006 1 commit
  23. 30 Jun, 2006 1 commit
  24. 24 Jun, 2005 1 commit