1. 04 Sep, 2019 1 commit
  2. 30 May, 2019 1 commit
  3. 31 Oct, 2017 1 commit
  4. 09 Jan, 2017 1 commit
  5. 23 Nov, 2016 1 commit
    • Javier Martinez Canillas's avatar
      spi: spi-axi: Fix module autoload · 01affe23
      Javier Martinez Canillas authored and Mark Brown's avatar Mark Brown committed
      
      
      If the driver is built as a module, autoload won't work because the module
      alias information is not filled. So user-space can't match the registered
      device with the corresponding module.
      
      Export the module alias information using the MODULE_DEVICE_TABLE() macro.
      
      Before this patch:
      
      $ modinfo drivers/spi/spi-axi-spi-engine.ko | grep alias
      $
      
      After this patch:
      
      $ modinfo drivers/spi/spi-axi-spi-engine.ko | grep alias
      alias:          of:N*T*Cadi,axi-spi-engine-1.00.aC*
      alias:          of:N*T*Cadi,axi-spi-engine-1.00.a
      Signed-off-by: default avatarJavier Martinez Canillas <javier@osg.samsung.com>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      01affe23
  6. 26 Apr, 2016 1 commit
  7. 05 Feb, 2016 1 commit
    • Lars-Peter Clausen's avatar
      spi: Add Analog Devices AXI SPI Engine controller support · b1353d1c
      Lars-Peter Clausen authored and Mark Brown's avatar Mark Brown committed
      This patch adds support for the AXI SPI Engine controller which is a FPGA
      soft-peripheral which is used in some of Analog Devices' reference designs.
      
      The AXI SPI Engine controller is part of the SPI Engine framework[1] and
      allows memory mapped access to the SPI Engine control bus. This allows it
      to be used as a general purpose software driven SPI controller. The SPI
      Engine in addition offers some optional advanced acceleration and
      offloading capabilities, which are not part of this patch though and will
      be introduced separately.
      
      At the core of the SPI Engine framework is a small sort of co-processor
      that accepts a command stream and turns the commands into low-level SPI
      transactions. Communication is done through three memory mapped FIFOs in
      the register map of the AXI SPI Engine peripheral. One FIFO for the command
      stream and one each for transmit and receive data.
      
      The driver translates a spi_message in a command stream and writes it to
      the peripheral which executes it asynchronously. This allows it to perform
      very precise timings which are required for some SPI slave devices to
      achieve maximum performance (e.g. analog-to-digital and digital-to-analog
      converters). The execution flow is synchronized to the host system by a
      special synchronize instruction which generates a interrupt.
      
      [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine
      
      Signed-off-by: default avatarLars-Peter Clausen <lars@metafoo.de>
      Signed-off-by: Mark Brown's avatarMark Brown <broonie@kernel.org>
      b1353d1c