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Commit 96cd17f4 authored by Siva Durga Prasad Paladugu's avatar Siva Durga Prasad Paladugu
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zynqmp: pm: Correct WDT clock database


WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL register, there can be only two
parents of WDT clock not three. Fix the same by correcting it's
parents in clock database.

Signed-off-by: default avatarTejas Patel <tejas.patel@xilinx.com>
Signed-off-by: default avatarSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: default avatarJolly Shah <jolly.shah@xilinx.com>
parent 6ad42b98
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