Commit 96cd17f4 authored by Siva Durga Prasad Paladugu's avatar Siva Durga Prasad Paladugu
Browse files

zynqmp: pm: Correct WDT clock database



WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL register, there can be only two
parents of WDT clock not three. Fix the same by correcting it's
parents in clock database.

Signed-off-by: default avatarTejas Patel <tejas.patel@xilinx.com>
Signed-off-by: default avatarSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: default avatarJolly Shah <jolly.shah@xilinx.com>
parent 6ad42b98
......@@ -2022,12 +2022,11 @@ static struct pm_clock clocks[] = {
},
[CLK_WDT] = {
.name = "wdt",
.control_reg = IOU_SLCR_WDT_CLK_SEL,
.control_reg = FPD_SLCR_WDT_CLK_SEL,
.status_reg = 0,
.parents = &((int32_t []) {
CLK_TOPSW_LSBUS,
EXT_CLK_SWDT0 | CLK_EXTERNAL_PARENT,
EXT_CLK_SWDT1 | CLK_EXTERNAL_PARENT,
CLK_NA_PARENT
}),
.nodes = &wdt_nodes,
......
......@@ -201,6 +201,7 @@
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
#define FPD_SLCR_BASEADDR U(0xFD610000)
#define IOU_SLCR_BASEADDR U(0xFF180000)
#define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000)
......@@ -325,7 +326,7 @@
#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108)
#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100)
/* Global general storage register base address */
#define GGS_BASEADDR (0xFFD80030U)
......
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