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tc0: architecture changes

Darryl Green requested to merge github/fork/uarif1/tc0_architecture_changes into master

Created by: uarif1

This include the following changes:

  • Memory and interrupt map changes
  • use UART0 from RoS AP memory map
  • Add a second scmi and mhuv2 channel
  • Change memory configuration from having ITC and DTC RAM to having just 1 RAM
  • Change processor from Cortex-M7 to Cortex-M3

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