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Optimize F32 <- QSI8D32 (LHS) x QSI4C32 (RHS) for SME

Gian Marco Iodice requested to merge mm_qsi8d32p_qsi4c32p_sme into main
  • GEMM and GEMV Micro-kernels to compute the matrix multiplication of dynamically quantized symmetric signed 8-bit integer with per-block quantization (QSI8D32) LHS matrix and quantized symmetric 4-bit signed integer with per-block quantization (QSI4C32) RHS matrix and the accumulation of the result into a single-precision (F32) output, optimized for SME2 technology.

Signed-off-by: Gian Marco Iodice gianmarco.iodice@arm.com

Signed-off-by: Anitha Raj anitha.raj@arm.com

Edited by Anitha Raj

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