Commit a508ea95 authored by Jean-Philippe Brucker's avatar Jean-Philippe Brucker Committed by Will Deacon
Browse files

virtio/pci: Use port I/O for configuration registers by default

Modern virtio PCI is allowed to use both memory and I/O BARs for the
config space, but legacy devices must use I/O for BAR0, as specified by
Virtio v1.0 cs04:

4.1.5.1.1.1 Legacy Interface: A Note on Device Layout Detection
"Transitional devices MUST expose the Legacy Interface in I/O space in
BAR0."

What virtio calls "I/O space" is most certainly port I/O, as hinted by the
discussion in 4.1.4 Virtio Structure PCI Capabilities, where it
distinguishes "memory BARs" from "I/O BARs". This is also the conclusion
made by SeaBIOS [1], which only looks for port I/O in BAR0 when driving a
transitional device.

I think MMIO was made the default by a463650c ("kvm tools: pci: add
MMIO interface to virtio-pci devices") to support ARM targets, but we
support PIO as well as MMIO nowadays. So let's make the legacy virtio
implementation comply with the specification and use port I/O for BAR0.

[1] https://patchwork.kernel.org/patch/10038927/



Signed-off-by: default avatarJean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent b7af514c
...@@ -450,10 +450,10 @@ int virtio_pci__init(struct kvm *kvm, void *dev, struct virtio_device *vdev, ...@@ -450,10 +450,10 @@ int virtio_pci__init(struct kvm *kvm, void *dev, struct virtio_device *vdev,
.class[2] = (class >> 16) & 0xff, .class[2] = (class >> 16) & 0xff,
.subsys_vendor_id = cpu_to_le16(PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET), .subsys_vendor_id = cpu_to_le16(PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET),
.subsys_id = cpu_to_le16(subsys_id), .subsys_id = cpu_to_le16(subsys_id),
.bar[0] = cpu_to_le32(vpci->mmio_addr .bar[0] = cpu_to_le32(vpci->port_addr
| PCI_BASE_ADDRESS_SPACE_MEMORY),
.bar[1] = cpu_to_le32(vpci->port_addr
| PCI_BASE_ADDRESS_SPACE_IO), | PCI_BASE_ADDRESS_SPACE_IO),
.bar[1] = cpu_to_le32(vpci->mmio_addr
| PCI_BASE_ADDRESS_SPACE_MEMORY),
.bar[2] = cpu_to_le32(vpci->msix_io_block .bar[2] = cpu_to_le32(vpci->msix_io_block
| PCI_BASE_ADDRESS_SPACE_MEMORY), | PCI_BASE_ADDRESS_SPACE_MEMORY),
.status = cpu_to_le16(PCI_STATUS_CAP_LIST), .status = cpu_to_le16(PCI_STATUS_CAP_LIST),
......
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