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  • Stephen Boyd's avatar
    clk: qcom: Fix PLL rate configurations · 5b6b7490
    Stephen Boyd authored
    Sometimes we need to program PLLs with a fixed rate
    configuration during driver probe. Doing this after we register
    the PLLs with the clock framework causes the common clock
    framework to assume the rate of the PLLs are 0. This causes all
    sorts of problems for rate recalculations because the common
    clock framework caches the rate once at registration time unless
    a flag is set to always recalculate the rates.
    Split the qcom_cc_probe() function into two pieces, map and
    everything else, so that drivers which need to configure some
    PLL rates or otherwise twiddle bits in the clock controller can
    do so before registering clocks. This allows us to properly
    detect the rates of PLLs that are programmed at boot.
    Fixes: 49fc825f
     "clk: qcom: Consolidate common probe code"
    Signed-off-by: default avatarStephen Boyd <>