Commit 92d7223a authored by Sinan Kaya's avatar Sinan Kaya Committed by Matt Turner
Browse files

alpha: io: reorder barriers to guarantee writeX() and iowriteX() ordering #2



memory-barriers.txt has been updated with the following requirement.

"When using writel(), a prior wmb() is not needed to guarantee that the
cache coherent memory writes have completed before writing to the MMIO
region."

Current writeX() and iowriteX() implementations on alpha are not
satisfying this requirement as the barrier is after the register write.

Move mb() in writeX() and iowriteX() functions to guarantee that HW
observes memory changes before performing register operations.

Signed-off-by: default avatarSinan Kaya <okaya@codeaurora.org>
Reported-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarMatt Turner <mattst88@gmail.com>
parent f5e82fa2
......@@ -37,20 +37,20 @@ unsigned int ioread32(void __iomem *addr)
void iowrite8(u8 b, void __iomem *addr)
{
IO_CONCAT(__IO_PREFIX,iowrite8)(b, addr);
mb();
IO_CONCAT(__IO_PREFIX,iowrite8)(b, addr);
}
void iowrite16(u16 b, void __iomem *addr)
{
IO_CONCAT(__IO_PREFIX,iowrite16)(b, addr);
mb();
IO_CONCAT(__IO_PREFIX,iowrite16)(b, addr);
}
void iowrite32(u32 b, void __iomem *addr)
{
IO_CONCAT(__IO_PREFIX,iowrite32)(b, addr);
mb();
IO_CONCAT(__IO_PREFIX,iowrite32)(b, addr);
}
EXPORT_SYMBOL(ioread8);
......@@ -176,26 +176,26 @@ u64 readq(const volatile void __iomem *addr)
void writeb(u8 b, volatile void __iomem *addr)
{
__raw_writeb(b, addr);
mb();
__raw_writeb(b, addr);
}
void writew(u16 b, volatile void __iomem *addr)
{
__raw_writew(b, addr);
mb();
__raw_writew(b, addr);
}
void writel(u32 b, volatile void __iomem *addr)
{
__raw_writel(b, addr);
mb();
__raw_writel(b, addr);
}
void writeq(u64 b, volatile void __iomem *addr)
{
__raw_writeq(b, addr);
mb();
__raw_writeq(b, addr);
}
EXPORT_SYMBOL(readb);
......
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